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The Versatile FPGA interrupt controller supports cascading interrupts, i.e. that its output is connected to the input of another interrupt controller. This makes it possible to pass a parent interrupt from the device tree and print it in the boot log if applicable. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
37 lines
1.5 KiB
Plaintext
37 lines
1.5 KiB
Plaintext
* ARM Versatile FPGA interrupt controller
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One or more FPGA IRQ controllers can be synthesized in an ARM reference board
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such as the Integrator or Versatile family. The output of these different
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controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
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instance can handle up to 32 interrupts.
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Required properties:
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- compatible: "arm,versatile-fpga-irq"
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- interrupt-controller: Identifies the node as an interrupt controller
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- #interrupt-cells: The number of cells to define the interrupts. Must be 1
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as the FPGA IRQ controller has no configuration options for interrupt
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sources. The cell is a u32 and defines the interrupt number.
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- reg: The register bank for the FPGA interrupt controller.
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- clear-mask: a u32 number representing the mask written to clear all IRQs
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on the controller at boot for example.
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- valid-mask: a u32 number representing a bit mask determining which of
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the interrupts are valid. Unconnected/unused lines are set to 0, and
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the system till not make it possible for devices to request these
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interrupts.
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Example:
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pic: pic@14000000 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x14000000 0x100>;
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clear-mask = <0xffffffff>;
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valid-mask = <0x003fffff>;
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};
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Optional properties:
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- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
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output is simply connected to the input of another IRQ controller,
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then the parent IRQ shall be specified in this property.
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