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76c9dd9dbd
This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DM644X
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include "pll.h"
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static const struct davinci_pll_clk_info dm644x_pll1_info = {
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.name = "pll1",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 1,
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.pllm_max = 32,
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.pllout_min_rate = 400000000,
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.pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
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.flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
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};
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SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
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clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
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clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
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clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
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clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
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davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
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return 0;
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}
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static const struct davinci_pll_clk_info dm644x_pll2_info = {
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.name = "pll2",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 1,
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.pllm_max = 32,
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.pllout_min_rate = 400000000,
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.pllout_max_rate = 900000000,
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.flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
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};
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
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SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
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int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
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davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
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return 0;
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}
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