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ac12cf85d6
* for-next/52-bit-kva: (25 commits) Support for 52-bit virtual addressing in kernel space * for-next/cpu-topology: (9 commits) Move CPU topology parsing into core code and add support for ACPI 6.3 * for-next/error-injection: (2 commits) Support for function error injection via kprobes * for-next/perf: (8 commits) Support for i.MX8 DDR PMU and proper SMMUv3 group validation * for-next/psci-cpuidle: (7 commits) Move PSCI idle code into a new CPUidle driver * for-next/rng: (4 commits) Support for 'rng-seed' property being passed in the devicetree * for-next/smpboot: (3 commits) Reduce fragility of secondary CPU bringup in debug configurations * for-next/tbi: (10 commits) Introduce new syscall ABI with relaxed requirements for pointer tags * for-next/tlbi: (6 commits) Handle spurious page faults arising from kernel space
350 lines
10 KiB
C
350 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/memory.h
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*
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* Copyright (C) 2000-2002 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* Note: this file should not be included by non-asm/.h files
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*/
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#ifndef __ASM_MEMORY_H
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#define __ASM_MEMORY_H
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#include <linux/compiler.h>
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#include <linux/const.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include <asm/bug.h>
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#include <asm/page-def.h>
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/*
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* Size of the PCI I/O space. This must remain a power of two so that
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* IO_SPACE_LIMIT acts as a mask for the low bits of I/O addresses.
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*/
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#define PCI_IO_SIZE SZ_16M
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/*
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* VMEMMAP_SIZE - allows the whole linear region to be covered by
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* a struct page array
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*
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* If we are configured with a 52-bit kernel VA then our VMEMMAP_SIZE
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* needs to cover the memory region from the beginning of the 52-bit
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* PAGE_OFFSET all the way to PAGE_END for 48-bit. This allows us to
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* keep a constant PAGE_OFFSET and "fallback" to using the higher end
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* of the VMEMMAP where 52-bit support is not available in hardware.
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*/
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#define VMEMMAP_SIZE ((_PAGE_END(VA_BITS_MIN) - PAGE_OFFSET) \
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>> (PAGE_SHIFT - STRUCT_PAGE_MAX_SHIFT))
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/*
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* PAGE_OFFSET - the virtual address of the start of the linear map, at the
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* start of the TTBR1 address space.
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* PAGE_END - the end of the linear map, where all other kernel mappings begin.
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* KIMAGE_VADDR - the virtual address of the start of the kernel image.
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* VA_BITS - the maximum number of bits for virtual addresses.
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*/
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#define VA_BITS (CONFIG_ARM64_VA_BITS)
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#define _PAGE_OFFSET(va) (-(UL(1) << (va)))
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#define PAGE_OFFSET (_PAGE_OFFSET(VA_BITS))
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#define KIMAGE_VADDR (MODULES_END)
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#define BPF_JIT_REGION_START (KASAN_SHADOW_END)
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#define BPF_JIT_REGION_SIZE (SZ_128M)
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#define BPF_JIT_REGION_END (BPF_JIT_REGION_START + BPF_JIT_REGION_SIZE)
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#define MODULES_END (MODULES_VADDR + MODULES_VSIZE)
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#define MODULES_VADDR (BPF_JIT_REGION_END)
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#define MODULES_VSIZE (SZ_128M)
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#define VMEMMAP_START (-VMEMMAP_SIZE - SZ_2M)
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#define PCI_IO_END (VMEMMAP_START - SZ_2M)
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#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
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#define FIXADDR_TOP (PCI_IO_START - SZ_2M)
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#if VA_BITS > 48
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#define VA_BITS_MIN (48)
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#else
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#define VA_BITS_MIN (VA_BITS)
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#endif
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#define _PAGE_END(va) (-(UL(1) << ((va) - 1)))
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#define KERNEL_START _text
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#define KERNEL_END _end
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#ifdef CONFIG_ARM64_VA_BITS_52
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#define MAX_USER_VA_BITS 52
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#else
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#define MAX_USER_VA_BITS VA_BITS
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#endif
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/*
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* Generic and tag-based KASAN require 1/8th and 1/16th of the kernel virtual
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* address space for the shadow region respectively. They can bloat the stack
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* significantly, so double the (minimum) stack size when they are in use.
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*/
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#ifdef CONFIG_KASAN
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#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL)
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#define KASAN_SHADOW_END ((UL(1) << (64 - KASAN_SHADOW_SCALE_SHIFT)) \
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+ KASAN_SHADOW_OFFSET)
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#define KASAN_THREAD_SHIFT 1
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#else
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#define KASAN_THREAD_SHIFT 0
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#define KASAN_SHADOW_END (_PAGE_END(VA_BITS_MIN))
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#endif /* CONFIG_KASAN */
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#define MIN_THREAD_SHIFT (14 + KASAN_THREAD_SHIFT)
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/*
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* VMAP'd stacks are allocated at page granularity, so we must ensure that such
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* stacks are a multiple of page size.
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*/
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#if defined(CONFIG_VMAP_STACK) && (MIN_THREAD_SHIFT < PAGE_SHIFT)
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#define THREAD_SHIFT PAGE_SHIFT
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#else
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#define THREAD_SHIFT MIN_THREAD_SHIFT
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#endif
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#if THREAD_SHIFT >= PAGE_SHIFT
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#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
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#endif
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#define THREAD_SIZE (UL(1) << THREAD_SHIFT)
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/*
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* By aligning VMAP'd stacks to 2 * THREAD_SIZE, we can detect overflow by
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* checking sp & (1 << THREAD_SHIFT), which we can do cheaply in the entry
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* assembly.
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*/
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#ifdef CONFIG_VMAP_STACK
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#define THREAD_ALIGN (2 * THREAD_SIZE)
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#else
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#define THREAD_ALIGN THREAD_SIZE
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#endif
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#define IRQ_STACK_SIZE THREAD_SIZE
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#define OVERFLOW_STACK_SIZE SZ_4K
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/*
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* Alignment of kernel segments (e.g. .text, .data).
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*/
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#if defined(CONFIG_DEBUG_ALIGN_RODATA)
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/*
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* 4 KB granule: 1 level 2 entry
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* 16 KB granule: 128 level 3 entries, with contiguous bit
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* 64 KB granule: 32 level 3 entries, with contiguous bit
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*/
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#define SEGMENT_ALIGN SZ_2M
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#else
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/*
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* 4 KB granule: 16 level 3 entries, with contiguous bit
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* 16 KB granule: 4 level 3 entries, without contiguous bit
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* 64 KB granule: 1 level 3 entry
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*/
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#define SEGMENT_ALIGN SZ_64K
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#endif
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/*
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* Memory types available.
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*/
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#define MT_DEVICE_nGnRnE 0
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#define MT_DEVICE_nGnRE 1
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#define MT_DEVICE_GRE 2
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#define MT_NORMAL_NC 3
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#define MT_NORMAL 4
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#define MT_NORMAL_WT 5
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/*
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* Memory types for Stage-2 translation
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*/
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#define MT_S2_NORMAL 0xf
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#define MT_S2_DEVICE_nGnRE 0x1
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/*
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* Memory types for Stage-2 translation when ID_AA64MMFR2_EL1.FWB is 0001
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* Stage-2 enforces Normal-WB and Device-nGnRE
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*/
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#define MT_S2_FWB_NORMAL 6
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#define MT_S2_FWB_DEVICE_nGnRE 1
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#ifdef CONFIG_ARM64_4K_PAGES
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#define IOREMAP_MAX_ORDER (PUD_SHIFT)
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#else
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#define IOREMAP_MAX_ORDER (PMD_SHIFT)
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#endif
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#ifndef __ASSEMBLY__
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extern u64 vabits_actual;
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#define PAGE_END (_PAGE_END(vabits_actual))
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#include <linux/bitops.h>
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#include <linux/mmdebug.h>
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extern s64 physvirt_offset;
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extern s64 memstart_addr;
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/* PHYS_OFFSET - the physical address of the start of memory. */
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#define PHYS_OFFSET ({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
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/* the virtual base of the kernel image (minus TEXT_OFFSET) */
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extern u64 kimage_vaddr;
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/* the offset between the kernel virtual and physical mappings */
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extern u64 kimage_voffset;
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static inline unsigned long kaslr_offset(void)
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{
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return kimage_vaddr - KIMAGE_VADDR;
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}
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/*
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* Allow all memory at the discovery stage. We will clip it later.
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*/
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#define MIN_MEMBLOCK_ADDR 0
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#define MAX_MEMBLOCK_ADDR U64_MAX
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/*
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* PFNs are used to describe any physical page; this means
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* PFN 0 == physical address 0.
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*
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* This is the PFN of the first RAM page in the kernel
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* direct-mapped view. We assume this is the first page
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* of RAM in the mem_map as well.
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*/
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#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
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/*
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* When dealing with data aborts, watchpoints, or instruction traps we may end
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* up with a tagged userland pointer. Clear the tag to get a sane pointer to
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* pass on to access_ok(), for instance.
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*/
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#define untagged_addr(addr) \
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((__force __typeof__(addr))sign_extend64((__force u64)(addr), 55))
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#ifdef CONFIG_KASAN_SW_TAGS
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#define __tag_shifted(tag) ((u64)(tag) << 56)
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#define __tag_reset(addr) untagged_addr(addr)
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#define __tag_get(addr) (__u8)((u64)(addr) >> 56)
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#else
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#define __tag_shifted(tag) 0UL
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#define __tag_reset(addr) (addr)
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#define __tag_get(addr) 0
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#endif /* CONFIG_KASAN_SW_TAGS */
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static inline const void *__tag_set(const void *addr, u8 tag)
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{
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u64 __addr = (u64)addr & ~__tag_shifted(0xff);
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return (const void *)(__addr | __tag_shifted(tag));
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}
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/*
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* Physical vs virtual RAM address space conversion. These are
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* private definitions which should NOT be used outside memory.h
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* files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
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*/
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/*
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* The linear kernel range starts at the bottom of the virtual address
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* space. Testing the top bit for the start of the region is a
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* sufficient check and avoids having to worry about the tag.
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*/
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#define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1)))
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#define __lm_to_phys(addr) (((addr) + physvirt_offset))
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#define __kimg_to_phys(addr) ((addr) - kimage_voffset)
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#define __virt_to_phys_nodebug(x) ({ \
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phys_addr_t __x = (phys_addr_t)(__tag_reset(x)); \
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__is_lm_address(__x) ? __lm_to_phys(__x) : __kimg_to_phys(__x); \
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})
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#define __pa_symbol_nodebug(x) __kimg_to_phys((phys_addr_t)(x))
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#ifdef CONFIG_DEBUG_VIRTUAL
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extern phys_addr_t __virt_to_phys(unsigned long x);
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extern phys_addr_t __phys_addr_symbol(unsigned long x);
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#else
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#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
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#define __phys_addr_symbol(x) __pa_symbol_nodebug(x)
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#endif /* CONFIG_DEBUG_VIRTUAL */
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#define __phys_to_virt(x) ((unsigned long)((x) - physvirt_offset))
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#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset))
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/*
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* Convert a page to/from a physical address
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*/
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#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page)))
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#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys)))
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/*
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* Note: Drivers should NOT use these. They are the wrong
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* translation for translating DMA addresses. Use the driver
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* DMA support - see dma-mapping.h.
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*/
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#define virt_to_phys virt_to_phys
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static inline phys_addr_t virt_to_phys(const volatile void *x)
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{
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return __virt_to_phys((unsigned long)(x));
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}
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#define phys_to_virt phys_to_virt
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static inline void *phys_to_virt(phys_addr_t x)
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{
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return (void *)(__phys_to_virt(x));
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}
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/*
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* Drivers should NOT use these either.
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*/
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#define __pa(x) __virt_to_phys((unsigned long)(x))
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#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
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#define __pa_nodebug(x) __virt_to_phys_nodebug((unsigned long)(x))
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#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
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#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
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#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys((unsigned long)(x)))
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#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x))
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/*
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* virt_to_page(x) convert a _valid_ virtual address to struct page *
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* virt_addr_valid(x) indicates whether a virtual address is valid
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*/
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#define ARCH_PFN_OFFSET ((unsigned long)PHYS_PFN_OFFSET)
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#if !defined(CONFIG_SPARSEMEM_VMEMMAP) || defined(CONFIG_DEBUG_VIRTUAL)
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#define virt_to_page(x) pfn_to_page(virt_to_pfn(x))
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#else
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#define page_to_virt(x) ({ \
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__typeof__(x) __page = x; \
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u64 __idx = ((u64)__page - VMEMMAP_START) / sizeof(struct page);\
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u64 __addr = PAGE_OFFSET + (__idx * PAGE_SIZE); \
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(void *)__tag_set((const void *)__addr, page_kasan_tag(__page));\
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})
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#define virt_to_page(x) ({ \
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u64 __idx = (__tag_reset((u64)x) - PAGE_OFFSET) / PAGE_SIZE; \
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u64 __addr = VMEMMAP_START + (__idx * sizeof(struct page)); \
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(struct page *)__addr; \
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})
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#endif /* !CONFIG_SPARSEMEM_VMEMMAP || CONFIG_DEBUG_VIRTUAL */
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#define virt_addr_valid(addr) ({ \
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__typeof__(addr) __addr = addr; \
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__is_lm_address(__addr) && pfn_valid(virt_to_pfn(__addr)); \
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})
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#endif /* !ASSEMBLY */
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/*
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* Given that the GIC architecture permits ITS implementations that can only be
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* configured with a LPI table address once, GICv3 systems with many CPUs may
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* end up reserving a lot of different regions after a kexec for their LPI
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* tables (one per CPU), as we are forced to reuse the same memory after kexec
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* (and thus reserve it persistently with EFI beforehand)
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*/
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#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS)
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# define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS + 1)
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#endif
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#include <asm-generic/memory_model.h>
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#endif /* __ASM_MEMORY_H */
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