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e84665c9cb
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips. This patch adds support
for multiple switch chips on a network interface.
An example topology for a 16-port device with an embedded CPU is as
follows:
+-----+ +--------+ +--------+
| |eth0 10| switch |9 10| switch |
| CPU +----------+ +-------+ |
| | | chip 0 | | chip 1 |
+-----+ +---++---+ +---++---+
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|| ||
||1000baseT ||1000baseT
||ports 1-8 ||ports 9-16
This requires a couple of interdependent changes in the DSA layer:
- The dsa platform driver data needs to be extended: there is still
only one netdevice per DSA driver instance (eth0 in the example
above), but each of the switch chips in the tree needs its own
mii_bus device pointer, MII management bus address, and port name
array. (include/net/dsa.h) The existing in-tree dsa users need
some small changes to deal with this. (arch/arm)
- The DSA and Ethertype DSA tagging modules need to be extended to
use the DSA device ID field on receive and demultiplex the packet
accordingly, and fill in the DSA device ID field on transmit
according to which switch chip the packet is heading to.
(net/dsa/tag_{dsa,edsa}.c)
- The concept of "CPU port", which is the switch chip port that the
CPU is connected to (port 10 on switch chip 0 in the example), needs
to be extended with the concept of "upstream port", which is the
port on the switch chip that will bring us one hop closer to the CPU
(port 10 for both switch chips in the example above).
- The dsa platform data needs to specify which ports on which switch
chips are links to other switch chips, so that we can enable DSA
tagging mode on them. (For inter-switch links, we always use
non-EtherType DSA tagging, since it has lower overhead. The CPU
link uses dsa or edsa tagging depending on what the 'root' switch
chip supports.) This is done by specifying "dsa" for the given
port in the port array.
- The dsa platform data needs to be extended with information on via
which port to reach any given switch chip from any given switch chip.
This info is specified via the per-switch chip data struct ->rtable[]
array, which gives the nexthop ports for each of the other switches
in the tree.
For the example topology above, the dsa platform data would look
something like this:
static struct dsa_chip_data sw[2] = {
{
.mii_bus = &foo,
.sw_addr = 1,
.port_names[0] = "p1",
.port_names[1] = "p2",
.port_names[2] = "p3",
.port_names[3] = "p4",
.port_names[4] = "p5",
.port_names[5] = "p6",
.port_names[6] = "p7",
.port_names[7] = "p8",
.port_names[9] = "dsa",
.port_names[10] = "cpu",
.rtable = (s8 []){ -1, 9, },
}, {
.mii_bus = &foo,
.sw_addr = 2,
.port_names[0] = "p9",
.port_names[1] = "p10",
.port_names[2] = "p11",
.port_names[3] = "p12",
.port_names[4] = "p13",
.port_names[5] = "p14",
.port_names[6] = "p15",
.port_names[7] = "p16",
.port_names[10] = "dsa",
.rtable = (s8 []){ 10, -1, },
},
},
static struct dsa_platform_data pd = {
.netdev = &foo,
.nr_switches = 2,
.sw = sw,
};
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
193 lines
4.7 KiB
C
193 lines
4.7 KiB
C
/*
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* arch/arm/mach-orion5x/wrt350n-v2-setup.c
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ethtool.h>
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#include <net/dsa.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <mach/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
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{ 0, MPP_GPIO }, /* Power LED green (0=on) */
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{ 1, MPP_GPIO }, /* Security LED (0=on) */
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{ 2, MPP_GPIO }, /* Internal Button (0=on) */
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{ 3, MPP_GPIO }, /* Reset Button (0=on) */
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{ 4, MPP_GPIO }, /* PCI int */
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{ 5, MPP_GPIO }, /* Power LED orange (0=on) */
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{ 6, MPP_GPIO }, /* USB LED (0=on) */
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{ 7, MPP_GPIO }, /* Wireless LED (0=on) */
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{ 8, MPP_UNUSED }, /* ??? */
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{ 9, MPP_GIGE }, /* GE_RXERR */
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{ 10, MPP_UNUSED }, /* ??? */
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{ 11, MPP_UNUSED }, /* ??? */
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{ 12, MPP_GIGE }, /* GE_TXD[4] */
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{ 13, MPP_GIGE }, /* GE_TXD[5] */
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{ 14, MPP_GIGE }, /* GE_TXD[6] */
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{ 15, MPP_GIGE }, /* GE_TXD[7] */
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{ 16, MPP_GIGE }, /* GE_RXD[4] */
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{ 17, MPP_GIGE }, /* GE_RXD[5] */
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{ 18, MPP_GIGE }, /* GE_RXD[6] */
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{ 19, MPP_GIGE }, /* GE_RXD[7] */
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{ -1 },
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};
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/*
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* 8M NOR flash Device bus boot chip select
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*/
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#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000
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#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M
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static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
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{
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.name = "kernel",
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.offset = 0x00000000,
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.size = 0x00760000,
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}, {
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.name = "rootfs",
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.offset = 0x001a0000,
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.size = 0x005c0000,
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}, {
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.name = "lang",
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.offset = 0x00760000,
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.size = 0x00040000,
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}, {
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.name = "nvram",
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.offset = 0x007a0000,
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.size = 0x00020000,
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}, {
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.name = "u-boot",
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.offset = 0x007c0000,
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.size = 0x00040000,
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},
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};
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static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
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.width = 1,
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.parts = wrt350n_v2_nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
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};
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static struct resource wrt350n_v2_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = WRT350N_V2_NOR_BOOT_BASE,
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.end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device wrt350n_v2_nor_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &wrt350n_v2_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &wrt350n_v2_nor_flash_resource,
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};
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static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct dsa_chip_data wrt350n_v2_switch_chip_data = {
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.port_names[0] = "lan2",
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.port_names[1] = "lan1",
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.port_names[2] = "wan",
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.port_names[3] = "cpu",
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.port_names[5] = "lan3",
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.port_names[7] = "lan4",
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};
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static struct dsa_platform_data wrt350n_v2_switch_plat_data = {
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.nr_chips = 1,
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.chip = &wrt350n_v2_switch_chip_data,
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};
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static void __init wrt350n_v2_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(wrt350n_v2_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_eth_init(&wrt350n_v2_eth_data);
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orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
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orion5x_uart0_init();
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orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
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WRT350N_V2_NOR_BOOT_SIZE);
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platform_device_register(&wrt350n_v2_nor_flash);
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}
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static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* Mini-PCI slot.
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*/
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if (slot == 7)
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return gpio_to_irq(4);
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return -1;
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}
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static struct hw_pci wrt350n_v2_pci __initdata = {
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.nr_controllers = 2,
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.swizzle = pci_std_swizzle,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = wrt350n_v2_pci_map_irq,
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};
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static int __init wrt350n_v2_pci_init(void)
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{
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if (machine_is_wrt350n_v2())
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pci_common_init(&wrt350n_v2_pci);
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return 0;
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}
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subsys_initcall(wrt350n_v2_pci_init);
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MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
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/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = wrt350n_v2_init,
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.map_io = orion5x_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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.fixup = tag_fixup_mem32,
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MACHINE_END
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