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Integrate the Common Platform Interrupt Controller (cp_intc) support into the low-level irq handling for davinci and similar platforms. Do it such that support for cp_intc and the original aintc can coexist in the same kernel binary. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
52 lines
1.3 KiB
ArmAsm
52 lines
1.3 KiB
ArmAsm
/*
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* Low-level IRQ helper macros for TI DaVinci-based platforms
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <mach/io.h>
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#include <mach/irqs.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =davinci_intc_base
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ldr \base, [\base]
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
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ldr \tmp, =davinci_intc_type
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ldr \tmp, [\tmp]
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cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
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beq 1001f
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#endif
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#if defined(CONFIG_AINTC)
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ldr \tmp, [\base, #0x14]
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movs \tmp, \tmp, lsr #2
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sub \irqnr, \tmp, #1
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b 1002f
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#endif
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#if defined(CONFIG_CP_INTC)
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1001: ldr \irqnr, [\base, #0x80] /* get irq number */
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and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
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mov \tmp, \irqnr, lsr #3
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and \tmp, \tmp, #0xfc
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add \tmp, \tmp, #0x280 /* get the register offset */
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ldr \irqstat, [\base, \tmp] /* get the intc status */
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cmp \irqstat, #0x0
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#endif
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1002:
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.endm
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.macro irq_prio_table
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.endm
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