Kan Liang d18216fafe perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids ... On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the count value is not correct. Update intel_spr_extra_regs[] to support them. Fixes: 61b985e3e7 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1624029174-122219-3-git-send-email-kan.liang@linux.intel.com		2021-06-23 18:30:55 +02:00
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amd	Handle power-gating of AMD IOMMU perf counters properly when they are used.	2021-05-09 13:00:26 -07:00
intel	perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids	2021-06-23 18:30:55 +02:00
zhaoxin	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
core.c	perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task	2021-06-17 14:11:47 +02:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Alder Lake CPU support	2021-04-19 20:03:29 +02:00
perf_event.h	perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task	2021-06-17 14:11:47 +02:00
probe.c	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
probe.h	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
rapl.c	perf/x86/rapl: Add support for Intel Alder Lake	2021-04-19 20:03:30 +02:00