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d0d42df2a4
* at91: (24 commits) [ARM] 4615/4: sam926[13]ek buttons updated [ARM] 4765/1: [AT91] AT91CAP9A-DK board support [ARM] 4764/1: [AT91] AT91CAP9 core support [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation [ARM] 4761/1: [AT91] Board-support for NEW_LEDs [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200 [ARM] 4759/1: [AT91] Buttons on CSB300 [ARM] 4758/1: [AT91] LEDs [ARM] 4757/1: [AT91] UART initialization [ARM] 4756/1: [AT91] Makefile cleanup [ARM] 4755/1: [AT91] NAND update [ARM] 4754/1: [AT91] SSC library support [ARM] 4753/1: [AT91] Use DMA_BIT_MASK [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9 [ARM] 4751/1: [AT91] ISI peripheral on SAM9263 [ARM] 4750/1: [AT91] STN LCD displays on SAM9261 [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY [ARM] 4646/1: AT91: configurable HZ, default to 128 [ARM] 4688/1: at91: speed-up irq processing [ARM] 4657/1: AT91: Header definition update ... * ep93xx: [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups [ARM] 4668/1: ep93xx: implement new GPIO API * iop: [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device [ARM] 4708/1: iop: update defconfigs for 2.6.24 * kprobes: ARM kprobes: let's enable it ARM kprobes: special hook for the kprobes breakpoint handler ARM kprobes: prevent some functions involved with kprobes from being probed ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack ARM kprobes: add the kprobes hook to the page fault handler ARM kprobes: core code ARM kprobes: instruction single-stepping support * ks8695: [ARM] 4603/1: KS8695: debugfs interface to view pin state [ARM] 4601/1: KS8695: PCI support * misc: [ARM] remove duplicate includes [ARM] CONFIG_DEBUG_STACK_USAGE [ARM] 4689/1: small comment wrap fix [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS [SERIAL] 21285: Report baud rate back via termios [ARM] Remove pointless casts from void pointers, [ARM] Misc minor interrupt handler cleanups [ARM] Remove at91_lcdc.h [ARM] ARRAY_SIZE() cleanup [ARM] Update mach-types * msm: [ARM] msm: dma support for MSM7X00A [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A) [ARM] msm: irq and timer support for ARCH_MSM7X00A [ARM] msm: core platform support for ARCH_MSM7X00A * s3c2410: (33 commits) [ARM] 4795/1: S3C244X: Add armclk and setparent call [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used. [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull() [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users [ARM] 4781/1: S3C24XX: DMA suspend and resume support [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call [ARM] 4778/1: S3C2412: Add armclk and init from DVS state [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected ... * sa1100: [ARM] sa1100: add clock source support * vfp: [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support [ARM] 4583/1: ARMv7: Add VFPv3 support [ARM] 4582/2: Add support for the common VFP subarchitecture
655 lines
17 KiB
Plaintext
655 lines
17 KiB
Plaintext
comment "Processor Type"
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config CPU_32
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bool
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default y
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# Select CPU types depending on the architecture selected. This selects
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# which CPUs we support in the kernel image, and the compiler instruction
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# optimiser behaviour.
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# ARM610
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config CPU_ARM610
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bool "Support ARM610 processor"
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depends on ARCH_RPC
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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help
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The ARM610 is the successor to the ARM3 processor
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and was produced by VLSI Technology Inc.
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Say Y if you want support for the ARM610 processor.
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Otherwise, say N.
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# ARM7TDMI
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config CPU_ARM7TDMI
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bool "Support ARM7TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM7TDMI processor.
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Otherwise, say N.
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# ARM710
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config CPU_ARM710
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bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
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default y if ARCH_CLPS7500
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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designed by Advanced RISC Machines Ltd. The ARM710 is the
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successor to the ARM610 processor. It was released in
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July 1994 by VLSI Technology Inc.
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Say Y if you want support for the ARM710 processor.
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Otherwise, say N.
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# ARM720T
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config CPU_ARM720T
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bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
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default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WT if MMU
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select CPU_TLB_V4WT if MMU
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help
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A 32-bit RISC processor with 8kByte Cache, Write Buffer and
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MMU built around an ARM7TDMI core.
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Say Y if you want support for the ARM720T processor.
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Otherwise, say N.
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# ARM740T
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config CPU_ARM740T
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bool "Support ARM740T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V3 # although the core is v4t
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select CPU_CP15_MPU
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help
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A 32-bit RISC processor with 8KB cache or 4KB variants,
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write buffer and MPU(Protection Unit) built around
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an ARM7TDMI core.
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Say Y if you want support for the ARM740T processor.
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Otherwise, say N.
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# ARM9TDMI
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config CPU_ARM9TDMI
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bool "Support ARM9TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_CACHE_V4
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help
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A 32-bit RISC microprocessor based on the ARM9 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM9TDMI processor.
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Otherwise, say N.
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# ARM920T
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config CPU_ARM920T
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bool "Support ARM920T processor"
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depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
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default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM920T is licensed to be produced by numerous vendors,
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and is used in the Maverick EP9312 and the Samsung S3C2410.
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More information on the Maverick EP9312 at
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<http://linuxdevices.com/products/PD2382866068.html>.
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Say Y if you want support for the ARM920T processor.
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Otherwise, say N.
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# ARM922T
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config CPU_ARM922T
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bool "Support ARM922T processor" if ARCH_INTEGRATOR
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depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
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default y if ARCH_LH7A40X || ARCH_KS8695
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM922T is a version of the ARM920T, but with smaller
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instruction and data caches. It is used in Altera's
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Excalibur XA device family and Micrel's KS8695 Centaur.
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Say Y if you want support for the ARM922T processor.
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Otherwise, say N.
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# ARM925T
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config CPU_ARM925T
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bool "Support ARM925T processor" if ARCH_OMAP1
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depends on ARCH_OMAP15XX
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default y if ARCH_OMAP15XX
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM925T is a mix between the ARM920T and ARM926T, but with
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different instruction and data caches. It is used in TI's OMAP
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device family.
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Say Y if you want support for the ARM925T processor.
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Otherwise, say N.
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# ARM926T
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config CPU_ARM926T
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bool "Support ARM926T processor"
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depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
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default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
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select CPU_32v5
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select CPU_ABRT_EV5TJ
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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This is a variant of the ARM920. It has slightly different
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instruction sequences for cache and TLB operations. Curiously,
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there is no documentation on it at the ARM corporate website.
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Say Y if you want support for the ARM926T processor.
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Otherwise, say N.
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# ARM940T
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config CPU_ARM940T
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bool "Support ARM940T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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help
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ARM940T is a member of the ARM9TDMI family of general-
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purpose microprocessors with MPU and separate 4KB
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instruction and 4KB data cases, each with a 4-word line
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length.
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Say Y if you want support for the ARM940T processor.
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Otherwise, say N.
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# ARM946E-S
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config CPU_ARM946E
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bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v5
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select CPU_ABRT_NOMMU
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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help
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ARM946E-S is a member of the ARM9E-S family of high-
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performance, 32-bit system-on-chip processor solutions.
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The TCM and ARMv5TE 32-bit instruction set is supported.
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Say Y if you want support for the ARM946E-S processor.
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Otherwise, say N.
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# ARM1020 - needs validating
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config CPU_ARM1020
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bool "Support ARM1020T (rev 0) processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1020 is the 32K cached version of the ARM10 processor,
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with an addition of a floating-point unit.
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Say Y if you want support for the ARM1020 processor.
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Otherwise, say N.
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# ARM1020E - needs validating
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config CPU_ARM1020E
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bool "Support ARM1020E processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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depends on n
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# ARM1022E
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config CPU_ARM1022
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bool "Support ARM1022E processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1022E is an implementation of the ARMv5TE architecture
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based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
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embedded trace macrocell, and a floating-point unit.
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Say Y if you want support for the ARM1022E processor.
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Otherwise, say N.
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# ARM1026EJ-S
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config CPU_ARM1026
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bool "Support ARM1026EJ-S processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
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based upon the ARM10 integer core.
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Say Y if you want support for the ARM1026EJ-S processor.
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Otherwise, say N.
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# SA110
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config CPU_SA110
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bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
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default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
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select CPU_32v3 if ARCH_RPC
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select CPU_32v4 if !ARCH_RPC
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WB if MMU
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help
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The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
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is available at five speeds ranging from 100 MHz to 233 MHz.
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More information is available at
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<http://developer.intel.com/design/strong/sa110.htm>.
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Say Y if you want support for the SA-110 processor.
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Otherwise, say N.
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# SA1100
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config CPU_SA1100
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bool
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depends on ARCH_SA1100
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default y
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WB if MMU
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# XScale
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config CPU_XSCALE
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bool
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depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
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default y
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WBI if MMU
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# XScale Core Version 3
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config CPU_XSC3
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bool
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depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
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default y
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WBI if MMU
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select IO_36
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# ARMv6
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config CPU_V6
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bool "Support ARM V6 processor"
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depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
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default y if ARCH_MX3
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default y if ARCH_MSM7X00A
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select CPU_32v6
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select CPU_ABRT_EV6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V6 if MMU
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# ARMv6k
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config CPU_32v6K
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bool "Support ARM V6K processor extensions" if !SMP
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depends on CPU_V6
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default y if SMP && !ARCH_MX3
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help
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Say Y here if your ARMv6 processor supports the 'K' extension.
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This enables the kernel to use some instructions not present
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on previous processors, and as such a kernel build with this
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enabled will not boot on processors with do not support these
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instructions.
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# ARMv7
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config CPU_V7
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bool "Support ARM V7 processor"
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depends on ARCH_INTEGRATOR
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select CPU_32v6K
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select CPU_32v7
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select CPU_ABRT_EV7
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select CPU_CACHE_V7
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select CPU_CACHE_VIPT
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V7 if MMU
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# Figure out what processor architecture version we should be using.
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# This defines the compiler instruction set which depends on the machine type.
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config CPU_32v3
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bool
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select TLS_REG_EMUL if SMP || !MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
|
|
|
config CPU_32v4
|
|
bool
|
|
select TLS_REG_EMUL if SMP || !MMU
|
|
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
|
|
|
config CPU_32v4T
|
|
bool
|
|
select TLS_REG_EMUL if SMP || !MMU
|
|
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
|
|
|
config CPU_32v5
|
|
bool
|
|
select TLS_REG_EMUL if SMP || !MMU
|
|
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
|
|
|
config CPU_32v6
|
|
bool
|
|
select TLS_REG_EMUL if !CPU_32v6K && !MMU
|
|
|
|
config CPU_32v7
|
|
bool
|
|
|
|
# The abort model
|
|
config CPU_ABRT_NOMMU
|
|
bool
|
|
|
|
config CPU_ABRT_EV4
|
|
bool
|
|
|
|
config CPU_ABRT_EV4T
|
|
bool
|
|
|
|
config CPU_ABRT_LV4T
|
|
bool
|
|
|
|
config CPU_ABRT_EV5T
|
|
bool
|
|
|
|
config CPU_ABRT_EV5TJ
|
|
bool
|
|
|
|
config CPU_ABRT_EV6
|
|
bool
|
|
|
|
config CPU_ABRT_EV7
|
|
bool
|
|
|
|
# The cache model
|
|
config CPU_CACHE_V3
|
|
bool
|
|
|
|
config CPU_CACHE_V4
|
|
bool
|
|
|
|
config CPU_CACHE_V4WT
|
|
bool
|
|
|
|
config CPU_CACHE_V4WB
|
|
bool
|
|
|
|
config CPU_CACHE_V6
|
|
bool
|
|
|
|
config CPU_CACHE_V7
|
|
bool
|
|
|
|
config CPU_CACHE_VIVT
|
|
bool
|
|
|
|
config CPU_CACHE_VIPT
|
|
bool
|
|
|
|
if MMU
|
|
# The copy-page model
|
|
config CPU_COPY_V3
|
|
bool
|
|
|
|
config CPU_COPY_V4WT
|
|
bool
|
|
|
|
config CPU_COPY_V4WB
|
|
bool
|
|
|
|
config CPU_COPY_V6
|
|
bool
|
|
|
|
# This selects the TLB model
|
|
config CPU_TLB_V3
|
|
bool
|
|
help
|
|
ARM Architecture Version 3 TLB.
|
|
|
|
config CPU_TLB_V4WT
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writethrough cache.
|
|
|
|
config CPU_TLB_V4WB
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writeback cache.
|
|
|
|
config CPU_TLB_V4WBI
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writeback cache and invalidate
|
|
instruction cache entry.
|
|
|
|
config CPU_TLB_V6
|
|
bool
|
|
|
|
config CPU_TLB_V7
|
|
bool
|
|
|
|
endif
|
|
|
|
config CPU_HAS_ASID
|
|
bool
|
|
help
|
|
This indicates whether the CPU has the ASID register; used to
|
|
tag TLB and possibly cache entries.
|
|
|
|
config CPU_CP15
|
|
bool
|
|
help
|
|
Processor has the CP15 register.
|
|
|
|
config CPU_CP15_MMU
|
|
bool
|
|
select CPU_CP15
|
|
help
|
|
Processor has the CP15 register, which has MMU related registers.
|
|
|
|
config CPU_CP15_MPU
|
|
bool
|
|
select CPU_CP15
|
|
help
|
|
Processor has the CP15 register, which has MPU related registers.
|
|
|
|
#
|
|
# CPU supports 36-bit I/O
|
|
#
|
|
config IO_36
|
|
bool
|
|
|
|
comment "Processor Features"
|
|
|
|
config ARM_THUMB
|
|
bool "Support Thumb user binaries"
|
|
depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
|
|
default y
|
|
help
|
|
Say Y if you want to include kernel support for running user space
|
|
Thumb binaries.
|
|
|
|
The Thumb instruction set is a compressed form of the standard ARM
|
|
instruction set resulting in smaller binaries at the expense of
|
|
slightly less efficient code.
|
|
|
|
If you don't know what this all is, saying Y is a safe choice.
|
|
|
|
config CPU_BIG_ENDIAN
|
|
bool "Build big-endian kernel"
|
|
depends on ARCH_SUPPORTS_BIG_ENDIAN
|
|
help
|
|
Say Y if you plan on running a kernel in big-endian mode.
|
|
Note that your board must be properly built and your board
|
|
port must properly enable any big-endian related features
|
|
of your chipset/board/processor.
|
|
|
|
config CPU_HIGH_VECTOR
|
|
depends on !MMU && CPU_CP15 && !CPU_ARM740T
|
|
bool "Select the High exception vector"
|
|
default n
|
|
help
|
|
Say Y here to select high exception vector(0xFFFF0000~).
|
|
The exception vector can be vary depending on the platform
|
|
design in nommu mode. If your platform needs to select
|
|
high exception vector, say Y.
|
|
Otherwise or if you are unsure, say N, and the low exception
|
|
vector (0x00000000~) will be used.
|
|
|
|
config CPU_ICACHE_DISABLE
|
|
bool "Disable I-Cache (I-bit)"
|
|
depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
|
|
help
|
|
Say Y here to disable the processor instruction cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_DISABLE
|
|
bool "Disable D-Cache (C-bit)"
|
|
depends on CPU_CP15
|
|
help
|
|
Say Y here to disable the processor data cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_SIZE
|
|
hex
|
|
depends on CPU_ARM740T || CPU_ARM946E
|
|
default 0x00001000 if CPU_ARM740T
|
|
default 0x00002000 # default size for ARM946E-S
|
|
help
|
|
Some cores are synthesizable to have various sized cache. For
|
|
ARM946E-S case, it can vary from 0KB to 1MB.
|
|
To support such cache operations, it is efficient to know the size
|
|
before compile time.
|
|
If your SoC is configured to have a different size, define the value
|
|
here with proper conditions.
|
|
|
|
config CPU_DCACHE_WRITETHROUGH
|
|
bool "Force write through D-cache"
|
|
depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
|
|
default y if CPU_ARM925T
|
|
help
|
|
Say Y here to use the data cache in writethrough mode. Unless you
|
|
specifically require this or are unsure, say N.
|
|
|
|
config CPU_CACHE_ROUND_ROBIN
|
|
bool "Round robin I and D cache replacement algorithm"
|
|
depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
|
|
help
|
|
Say Y here to use the predictable round-robin cache replacement
|
|
policy. Unless you specifically require this or are unsure, say N.
|
|
|
|
config CPU_BPREDICT_DISABLE
|
|
bool "Disable branch prediction"
|
|
depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
|
|
help
|
|
Say Y here to disable branch prediction. If unsure, say N.
|
|
|
|
config TLS_REG_EMUL
|
|
bool
|
|
help
|
|
An SMP system using a pre-ARMv6 processor (there are apparently
|
|
a few prototypes like that in existence) and therefore access to
|
|
that required register must be emulated.
|
|
|
|
config HAS_TLS_REG
|
|
bool
|
|
depends on !TLS_REG_EMUL
|
|
default y if SMP || CPU_32v7
|
|
help
|
|
This selects support for the CP15 thread register.
|
|
It is defined to be available on some ARMv6 processors (including
|
|
all SMP capable ARMv6's) or later processors. User space may
|
|
assume directly accessing that register and always obtain the
|
|
expected value only on ARMv7 and above.
|
|
|
|
config NEEDS_SYSCALL_FOR_CMPXCHG
|
|
bool
|
|
help
|
|
SMP on a pre-ARMv6 processor? Well OK then.
|
|
Forget about fast user space cmpxchg support.
|
|
It is just not possible.
|
|
|
|
config OUTER_CACHE
|
|
bool
|
|
default n
|
|
|
|
config CACHE_L2X0
|
|
bool
|
|
select OUTER_CACHE
|