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8700eee627
This patch adds the following property for arc_emac. 1) phy-reset-gpios: The phy-reset-gpio is an optional property for arc emac device tree boot. Change the binding document to match the driver code. 2) phy-reset-duration: Different boards may require different phy reset duration. Add property phy-reset-duration for device tree probe, so that the boards that need a longer reset duration can specify it in their device tree. Anyway, we can add the above property for arc emac. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: netdev@vger.kernel.org Cc: "David S. Miller" <davem@davemloft.net> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc; Alexander Kochetkov <al.kochet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
* Synopsys ARC EMAC 10/100 Ethernet driver (EMAC)
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Required properties:
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- compatible: Should be "snps,arc-emac"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the EMAC interrupts
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- max-speed: see ethernet.txt file in the same directory.
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- phy: see ethernet.txt file in the same directory.
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Optional properties:
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- phy-reset-gpios : Should specify the gpio for phy reset
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- phy-reset-duration : Reset duration in milliseconds. Should present
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only if property "phy-reset-gpios" is available. Missing the property
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will have the duration be 1 millisecond. Numbers greater than 1000 are
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invalid and 1 millisecond will be used instead.
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Clock handling:
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The clock frequency is needed to calculate and set polling period of EMAC.
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It must be provided by one of:
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- clock-frequency: CPU frequency.
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- clocks: reference to the clock supplying the EMAC.
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Child nodes of the driver are the individual PHY devices connected to the
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MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
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Examples:
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ethernet@c0fc2000 {
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compatible = "snps,arc-emac";
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reg = <0xc0fc2000 0x3c>;
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interrupts = <6>;
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mac-address = [ 00 11 22 33 44 55 ];
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clock-frequency = <80000000>;
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/* or */
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clocks = <&emac_clock>;
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max-speed = <100>;
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phy = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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