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5b40baee4a
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
74 lines
1.6 KiB
Plaintext
74 lines
1.6 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Armada 370 and XP SoC";
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compatible = "marvell,armada_370_xp";
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cpus {
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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};
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};
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mpic: interrupt-controller@d0020000 {
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compatible = "marvell,mpic";
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&mpic>;
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ranges;
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serial@d0012000 {
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compatible = "ns16550";
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reg = <0xd0012000 0x100>;
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reg-shift = <2>;
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interrupts = <41>;
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status = "disabled";
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};
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serial@d0012100 {
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compatible = "ns16550";
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reg = <0xd0012100 0x100>;
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reg-shift = <2>;
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interrupts = <42>;
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status = "disabled";
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};
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timer@d0020300 {
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compatible = "marvell,armada-370-xp-timer";
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reg = <0xd0020300 0x30>;
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interrupts = <37>, <38>, <39>, <40>;
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};
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addr-decoding@d0020000 {
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compatible = "marvell,armada-addr-decoding-controller";
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reg = <0xd0020000 0x258>;
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};
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};
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};
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