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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
605 lines
13 KiB
C
605 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*
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* Author: Baoyou Xie <baoyou.xie@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define REG_CMD 0x04
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#define REG_DEVADDR_H 0x0C
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#define REG_DEVADDR_L 0x10
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#define REG_CLK_DIV_FS 0x14
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#define REG_CLK_DIV_HS 0x18
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#define REG_WRCONF 0x1C
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#define REG_RDCONF 0x20
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#define REG_DATA 0x24
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#define REG_STAT 0x28
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#define I2C_STOP 0
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#define I2C_MASTER BIT(0)
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#define I2C_ADDR_MODE_TEN BIT(1)
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#define I2C_IRQ_MSK_ENABLE BIT(3)
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#define I2C_RW_READ BIT(4)
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#define I2C_CMB_RW_EN BIT(5)
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#define I2C_START BIT(6)
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#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
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#define I2C_ADDR_LOW_SHIFT 0
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#define I2C_ADDR_HI_MASK GENMASK(2, 0)
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#define I2C_ADDR_HI_SHIFT 7
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#define I2C_WFIFO_RESET BIT(7)
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#define I2C_RFIFO_RESET BIT(7)
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#define I2C_IRQ_ACK_CLEAR BIT(7)
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#define I2C_INT_MASK GENMASK(6, 0)
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#define I2C_TRANS_DONE BIT(0)
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#define I2C_SR_EDEVICE BIT(1)
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#define I2C_SR_EDATA BIT(2)
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#define I2C_FIFO_MAX 16
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#define I2C_TIMEOUT msecs_to_jiffies(1000)
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#define DEV(i2c) ((i2c)->adap.dev.parent)
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struct zx2967_i2c {
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struct i2c_adapter adap;
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struct clk *clk;
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struct completion complete;
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u32 clk_freq;
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void __iomem *reg_base;
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size_t residue;
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int irq;
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int msg_rd;
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u8 *cur_trans;
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u8 access_cnt;
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int error;
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};
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static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
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u32 val, unsigned long reg)
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{
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writel_relaxed(val, i2c->reg_base + reg);
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}
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static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
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{
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return readl_relaxed(i2c->reg_base + reg);
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}
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static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
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void *data, unsigned long reg, int len)
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{
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writesb(i2c->reg_base + reg, data, len);
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}
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static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
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void *data, unsigned long reg, int len)
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{
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readsb(i2c->reg_base + reg, data, len);
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}
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static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
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{
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u32 status;
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u32 ctl;
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status = zx2967_i2c_readl(i2c, REG_STAT);
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status |= I2C_IRQ_ACK_CLEAR;
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zx2967_i2c_writel(i2c, status, REG_STAT);
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ctl = zx2967_i2c_readl(i2c, REG_CMD);
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if (i2c->msg_rd)
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ctl |= I2C_RW_READ;
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else
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ctl &= ~I2C_RW_READ;
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ctl &= ~I2C_CMB_RW_EN;
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ctl |= I2C_START;
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zx2967_i2c_writel(i2c, ctl, REG_CMD);
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}
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static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
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{
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u32 offset;
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u32 val;
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if (i2c->msg_rd) {
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offset = REG_RDCONF;
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val = I2C_RFIFO_RESET;
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} else {
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offset = REG_WRCONF;
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val = I2C_WFIFO_RESET;
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}
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val |= zx2967_i2c_readl(i2c, offset);
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zx2967_i2c_writel(i2c, val, offset);
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}
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static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
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{
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u8 val[I2C_FIFO_MAX] = {0};
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int i;
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if (size > I2C_FIFO_MAX) {
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dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
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size, I2C_FIFO_MAX);
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return -EINVAL;
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}
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zx2967_i2c_readsb(i2c, val, REG_DATA, size);
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for (i = 0; i < size; i++) {
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*i2c->cur_trans++ = val[i];
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i2c->residue--;
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}
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barrier();
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return 0;
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}
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static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
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{
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size_t residue = i2c->residue;
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u8 *buf = i2c->cur_trans;
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if (residue == 0) {
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dev_err(DEV(i2c), "residue is %d\n", (int)residue);
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return -EINVAL;
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}
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if (residue <= I2C_FIFO_MAX) {
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zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
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/* Again update before writing to FIFO to make sure isr sees. */
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i2c->residue = 0;
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i2c->cur_trans = NULL;
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} else {
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zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
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i2c->residue -= I2C_FIFO_MAX;
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i2c->cur_trans += I2C_FIFO_MAX;
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}
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barrier();
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return 0;
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}
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static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
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{
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u32 val;
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u32 clk_div;
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val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
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zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
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zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
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zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
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zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
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zx2967_i2c_writel(i2c, 1, REG_RDCONF);
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zx2967_i2c_flush_fifos(i2c);
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return 0;
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}
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static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
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{
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u32 status;
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status = zx2967_i2c_readl(i2c, REG_STAT);
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status |= I2C_IRQ_ACK_CLEAR;
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zx2967_i2c_writel(i2c, status, REG_STAT);
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}
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static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
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{
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u32 status;
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struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
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status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
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zx2967_i2c_isr_clr(i2c);
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if (status & I2C_SR_EDEVICE)
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i2c->error = -ENXIO;
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else if (status & I2C_SR_EDATA)
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i2c->error = -EIO;
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else if (status & I2C_TRANS_DONE)
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i2c->error = 0;
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else
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goto done;
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complete(&i2c->complete);
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done:
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return IRQ_HANDLED;
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}
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static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
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{
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u16 val;
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val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
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zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
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val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
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zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
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if (val)
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val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
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else
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val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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}
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static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
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{
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unsigned long time_left;
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int rd = i2c->msg_rd;
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int ret;
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reinit_completion(&i2c->complete);
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if (rd) {
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zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
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} else {
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ret = zx2967_i2c_fill_tx_fifo(i2c);
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if (ret)
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return ret;
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}
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zx2967_i2c_start_ctrl(i2c);
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time_left = wait_for_completion_timeout(&i2c->complete,
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I2C_TIMEOUT);
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if (time_left == 0)
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return -ETIMEDOUT;
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if (i2c->error)
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return i2c->error;
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return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
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}
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static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
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struct i2c_msg *msg)
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{
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int ret;
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int i;
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zx2967_i2c_flush_fifos(i2c);
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i2c->cur_trans = msg->buf;
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i2c->residue = msg->len;
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i2c->access_cnt = msg->len / I2C_FIFO_MAX;
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i2c->msg_rd = msg->flags & I2C_M_RD;
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for (i = 0; i < i2c->access_cnt; i++) {
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ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
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if (ret)
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return ret;
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}
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if (i2c->residue > 0) {
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ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
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if (ret)
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return ret;
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}
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i2c->residue = 0;
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i2c->access_cnt = 0;
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return 0;
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}
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static int zx2967_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
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int ret;
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int i;
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zx2967_set_addr(i2c, msgs->addr);
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for (i = 0; i < num; i++) {
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ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
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if (ret)
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return ret;
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}
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return num;
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}
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static void
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zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
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char read_write, u8 command, int size,
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union i2c_smbus_data *data)
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{
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u32 val;
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val = zx2967_i2c_readl(i2c, REG_RDCONF);
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val |= I2C_RFIFO_RESET;
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zx2967_i2c_writel(i2c, val, REG_RDCONF);
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zx2967_set_addr(i2c, addr);
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val = zx2967_i2c_readl(i2c, REG_CMD);
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val &= ~I2C_RW_READ;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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switch (size) {
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case I2C_SMBUS_BYTE:
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zx2967_i2c_writel(i2c, command, REG_DATA);
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break;
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case I2C_SMBUS_BYTE_DATA:
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zx2967_i2c_writel(i2c, command, REG_DATA);
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if (read_write == I2C_SMBUS_WRITE)
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zx2967_i2c_writel(i2c, data->byte, REG_DATA);
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break;
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case I2C_SMBUS_WORD_DATA:
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zx2967_i2c_writel(i2c, command, REG_DATA);
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if (read_write == I2C_SMBUS_WRITE) {
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zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
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zx2967_i2c_writel(i2c, (data->word & 0xff),
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REG_DATA);
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}
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break;
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}
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}
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static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
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union i2c_smbus_data *data)
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{
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unsigned long time_left;
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u8 buf[2];
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u32 val;
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reinit_completion(&i2c->complete);
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val = zx2967_i2c_readl(i2c, REG_CMD);
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val |= I2C_CMB_RW_EN;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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val = zx2967_i2c_readl(i2c, REG_CMD);
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val |= I2C_START;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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time_left = wait_for_completion_timeout(&i2c->complete,
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I2C_TIMEOUT);
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if (time_left == 0)
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return -ETIMEDOUT;
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if (i2c->error)
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return i2c->error;
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switch (size) {
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case I2C_SMBUS_BYTE:
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case I2C_SMBUS_BYTE_DATA:
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val = zx2967_i2c_readl(i2c, REG_DATA);
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data->byte = val;
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break;
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case I2C_SMBUS_WORD_DATA:
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case I2C_SMBUS_PROC_CALL:
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buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
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buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
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data->word = (buf[0] << 8) | buf[1];
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
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{
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unsigned long time_left;
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u32 val;
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reinit_completion(&i2c->complete);
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val = zx2967_i2c_readl(i2c, REG_CMD);
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val |= I2C_START;
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zx2967_i2c_writel(i2c, val, REG_CMD);
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time_left = wait_for_completion_timeout(&i2c->complete,
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I2C_TIMEOUT);
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if (time_left == 0)
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return -ETIMEDOUT;
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if (i2c->error)
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return i2c->error;
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return 0;
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}
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static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size, union i2c_smbus_data *data)
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{
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struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
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if (size == I2C_SMBUS_QUICK)
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read_write = I2C_SMBUS_WRITE;
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switch (size) {
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case I2C_SMBUS_QUICK:
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case I2C_SMBUS_BYTE:
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case I2C_SMBUS_BYTE_DATA:
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case I2C_SMBUS_WORD_DATA:
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zx2967_smbus_xfer_prepare(i2c, addr, read_write,
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command, size, data);
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break;
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default:
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return -EOPNOTSUPP;
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}
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if (read_write == I2C_SMBUS_READ)
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return zx2967_smbus_xfer_read(i2c, size, data);
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return zx2967_smbus_xfer_write(i2c);
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}
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static u32 zx2967_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C |
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I2C_FUNC_SMBUS_QUICK |
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I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA |
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I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA |
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I2C_FUNC_SMBUS_PROC_CALL |
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I2C_FUNC_SMBUS_I2C_BLOCK;
|
|
}
|
|
|
|
static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
|
|
{
|
|
struct zx2967_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
i2c_mark_adapter_suspended(&i2c->adap);
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused zx2967_i2c_resume(struct device *dev)
|
|
{
|
|
struct zx2967_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
clk_prepare_enable(i2c->clk);
|
|
i2c_mark_adapter_resumed(&i2c->adap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
|
|
zx2967_i2c_suspend, zx2967_i2c_resume);
|
|
|
|
static const struct i2c_algorithm zx2967_i2c_algo = {
|
|
.master_xfer = zx2967_i2c_xfer,
|
|
.smbus_xfer = zx2967_smbus_xfer,
|
|
.functionality = zx2967_i2c_func,
|
|
};
|
|
|
|
static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
|
|
.flags = I2C_AQ_NO_ZERO_LEN,
|
|
};
|
|
|
|
static const struct of_device_id zx2967_i2c_of_match[] = {
|
|
{ .compatible = "zte,zx296718-i2c", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
|
|
|
|
static int zx2967_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct zx2967_i2c *i2c;
|
|
void __iomem *reg_base;
|
|
struct resource *res;
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
reg_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(reg_base))
|
|
return PTR_ERR(reg_base);
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&pdev->dev, "missing controller clock");
|
|
return PTR_ERR(clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable i2c_clk\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = device_property_read_u32(&pdev->dev, "clock-frequency",
|
|
&i2c->clk_freq);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "missing clock-frequency");
|
|
return ret;
|
|
}
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
i2c->irq = ret;
|
|
i2c->reg_base = reg_base;
|
|
i2c->clk = clk;
|
|
|
|
init_completion(&i2c->complete);
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
ret = zx2967_i2c_reset_hardware(i2c);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to initialize i2c controller\n");
|
|
goto err_clk_unprepare;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, i2c->irq,
|
|
zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
|
|
goto err_clk_unprepare;
|
|
}
|
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
strlcpy(i2c->adap.name, "zx2967 i2c adapter",
|
|
sizeof(i2c->adap.name));
|
|
i2c->adap.algo = &zx2967_i2c_algo;
|
|
i2c->adap.quirks = &zx2967_i2c_quirks;
|
|
i2c->adap.nr = pdev->id;
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
|
|
|
ret = i2c_add_numbered_adapter(&i2c->adap);
|
|
if (ret)
|
|
goto err_clk_unprepare;
|
|
|
|
return 0;
|
|
|
|
err_clk_unprepare:
|
|
clk_disable_unprepare(i2c->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int zx2967_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver zx2967_i2c_driver = {
|
|
.probe = zx2967_i2c_probe,
|
|
.remove = zx2967_i2c_remove,
|
|
.driver = {
|
|
.name = "zx2967_i2c",
|
|
.of_match_table = zx2967_i2c_of_match,
|
|
.pm = &zx2967_i2c_dev_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(zx2967_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
|
|
MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
|
|
MODULE_LICENSE("GPL v2");
|