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Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs ipe_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_IPE(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate ipe_clks[] = {
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GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
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GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
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GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
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GATE_IPE(CLK_IPESYS_TOP, "ipesys_top", "top_ipe", 3),
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GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
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};
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static const struct mtk_clk_desc ipe_desc = {
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.clks = ipe_clks,
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.num_clks = ARRAY_SIZE(ipe_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_ipe[] = {
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{ .compatible = "mediatek,mt8188-ipesys", .data = &ipe_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ipe);
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static struct platform_driver clk_mt8188_ipe_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-ipe",
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.of_match_table = of_match_clk_mt8188_ipe,
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},
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};
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module_platform_driver(clk_mt8188_ipe_drv);
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MODULE_LICENSE("GPL");
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