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Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
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* Author: Jianhui Zhao <zhaojh329@gmail.com>
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* Author: Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mediatek,mt7981-clk.h>
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static const struct mtk_gate_regs sgmii0_cg_regs = {
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.set_ofs = 0xE4,
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.clr_ofs = 0xE4,
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.sta_ofs = 0xE4,
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};
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#define GATE_SGMII0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &sgmii0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate sgmii0_clks[] __initconst = {
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GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
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GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
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GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
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GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
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};
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static const struct mtk_gate_regs sgmii1_cg_regs = {
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.set_ofs = 0xE4,
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.clr_ofs = 0xE4,
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.sta_ofs = 0xE4,
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};
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#define GATE_SGMII1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &sgmii1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate sgmii1_clks[] __initconst = {
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GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
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GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
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GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
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GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
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};
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static const struct mtk_gate_regs eth_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x30,
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.sta_ofs = 0x30,
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};
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#define GATE_ETH(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = ð_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate eth_clks[] __initconst = {
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GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
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GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
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GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
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GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
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};
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static const struct mtk_clk_desc eth_desc = {
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.clks = eth_clks,
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.num_clks = ARRAY_SIZE(eth_clks),
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};
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static const struct mtk_clk_desc sgmii0_desc = {
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.clks = sgmii0_clks,
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.num_clks = ARRAY_SIZE(sgmii0_clks),
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};
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static const struct mtk_clk_desc sgmii1_desc = {
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.clks = sgmii1_clks,
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.num_clks = ARRAY_SIZE(sgmii1_clks),
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};
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static const struct of_device_id of_match_clk_mt7981_eth[] = {
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{ .compatible = "mediatek,mt7981-ethsys", .data = ð_desc },
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{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
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{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_eth);
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static struct platform_driver clk_mt7981_eth_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt7981-eth",
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.of_match_table = of_match_clk_mt7981_eth,
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},
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};
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module_platform_driver(clk_mt7981_eth_drv);
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MODULE_LICENSE("GPL");
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