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System runs at minimum performance, once powercap RAPL package domain enabled flag is changed from 1 to 0 to 1. Setting RAPL package domain enabled flag to 0, results in setting of power limit 4 (PL4) MSR 0x601 to 0. This implies disabling PL4 limit. The PL4 limit controls the peak power. So setting 0, results in some undesirable performance, which depends on hardware implementation. Even worse, when the enabled flag is set to 1 again. This will set PL4 MSR value to 0x01, which means reduce peak power to 0.125W. This will force system to run at the lowest possible performance on every PL4 supported system. Setting enabled flag should only affect the "enable" bit, not other bits. Here it is changing power limit. This is caused by a change which assumes that there is an enable bit in the PL4 MSR like other power limits. Although PL4 enable/disable bit is present with TPMI RAPL interface, it is not present with the MSR interface. There is a rapl_primitive_info defined for non existent PL4 enable bit and then it is used with the commit |
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| .. | ||
| arm_scmi_powercap.c | ||
| dtpm_cpu.c | ||
| dtpm_devfreq.c | ||
| dtpm_subsys.h | ||
| dtpm.c | ||
| idle_inject.c | ||
| intel_rapl_common.c | ||
| intel_rapl_msr.c | ||
| intel_rapl_tpmi.c | ||
| Kconfig | ||
| Makefile | ||
| powercap_sys.c | ||