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64f1da10ca
In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.
This patch fixes the following warning:
drivers/mtd/nand/raw/diskonchip.c: In function ‘doc_probe’:
./include/linux/printk.h:303:2: warning: this statement may fall through [-Wimplicit-fallthrough=]
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/nand/raw/diskonchip.c:1479:4: note: in expansion of macro ‘pr_err’
pr_err("DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n");
^~~~~~
drivers/mtd/nand/raw/diskonchip.c:1480:3: note: here
default:
^~~~~~~
drivers/mtd/nand/raw/nandsim.c: In function ‘ns_init_module’:
drivers/mtd/nand/raw/nandsim.c:2254:22: warning: this statement may fall through [-Wimplicit-fallthrough=]
chip->bbt_options |= NAND_BBT_NO_OOB;
drivers/mtd/nand/raw/nandsim.c:2255:2: note: here
case 1:
^~~~
drivers/mtd/nand/raw/nuc900_nand.c: In function ‘nuc900_nand_command_lp’:
./arch/x86/include/asm/io.h:91:22: warning: this statement may fall through [-Wimplicit-fallthrough=]
#define __raw_writel __writel
drivers/mtd/nand/raw/nuc900_nand.c:52:2: note: in expansion of macro ‘__raw_writel’
__raw_writel((val), (dev)->reg + REG_SMCMD)
^~~~~~~~~~~~
drivers/mtd/nand/raw/nuc900_nand.c:196:3: note: in expansion of macro ‘write_cmd_reg’
write_cmd_reg(nand, NAND_CMD_READSTART);
^~~~~~~~~~~~~
drivers/mtd/nand/raw/nuc900_nand.c:197:2: note: here
default:
^~~~~~~
drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_restore’:
drivers/mtd/nand/raw/omap_elm.c:512:4: warning: this statement may fall through [-Wimplicit-fallthrough=]
elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
regs->elm_syndrome_fragment_4[i]);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/nand/raw/omap_elm.c:514:3: note: here
case BCH8_ECC:
^~~~
drivers/mtd/nand/raw/omap_elm.c:517:4: warning: this statement may fall through [-Wimplicit-fallthrough=]
elm_write_reg(info, ELM_SYNDROME_FRAGMENT_2 + offset,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
regs->elm_syndrome_fragment_2[i]);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/nand/raw/omap_elm.c:519:3: note: here
case BCH4_ECC:
^~~~
drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_save’:
drivers/mtd/nand/raw/omap_elm.c:466:37: warning: this statement may fall through [-Wimplicit-fallthrough=]
regs->elm_syndrome_fragment_4[i] = elm_read_reg(info,
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
ELM_SYNDROME_FRAGMENT_4 + offset);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/nand/raw/omap_elm.c:468:3: note: here
case BCH8_ECC:
^~~~
drivers/mtd/nand/raw/omap_elm.c:471:37: warning: this statement may fall through [-Wimplicit-fallthrough=]
regs->elm_syndrome_fragment_2[i] = elm_read_reg(info,
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
ELM_SYNDROME_FRAGMENT_2 + offset);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mtd/nand/raw/omap_elm.c:473:3: note: here
case BCH4_ECC:
^~~~
Warning level 3 was used: -Wimplicit-fallthrough=3
This patch is part of the ongoing efforts to enabling
-Wimplicit-fallthrough.
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
309 lines
6.8 KiB
C
309 lines
6.8 KiB
C
/*
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* Copyright © 2009 Nuvoton technology corporation.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation;version 2 of the License.
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*
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#define REG_FMICSR 0x00
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#define REG_SMCSR 0xa0
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#define REG_SMISR 0xac
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#define REG_SMCMD 0xb0
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#define REG_SMADDR 0xb4
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#define REG_SMDATA 0xb8
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#define RESET_FMI 0x01
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#define NAND_EN 0x08
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#define READYBUSY (0x01 << 18)
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#define SWRST 0x01
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#define PSIZE (0x01 << 3)
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#define DMARWEN (0x03 << 1)
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#define BUSWID (0x01 << 4)
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#define ECC4EN (0x01 << 5)
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#define WP (0x01 << 24)
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#define NANDCS (0x01 << 25)
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#define ENDADDR (0x01 << 31)
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#define read_data_reg(dev) \
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__raw_readl((dev)->reg + REG_SMDATA)
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#define write_data_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMDATA)
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#define write_cmd_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMCMD)
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#define write_addr_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMADDR)
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struct nuc900_nand {
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struct nand_chip chip;
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void __iomem *reg;
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struct clk *clk;
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spinlock_t lock;
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};
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static inline struct nuc900_nand *mtd_to_nuc900(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct nuc900_nand, chip);
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}
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static const struct mtd_partition partitions[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024
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},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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}
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};
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static unsigned char nuc900_nand_read_byte(struct nand_chip *chip)
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{
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unsigned char ret;
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struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
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ret = (unsigned char)read_data_reg(nand);
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return ret;
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}
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static void nuc900_nand_read_buf(struct nand_chip *chip,
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unsigned char *buf, int len)
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{
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int i;
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struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
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for (i = 0; i < len; i++)
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buf[i] = (unsigned char)read_data_reg(nand);
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}
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static void nuc900_nand_write_buf(struct nand_chip *chip,
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const unsigned char *buf, int len)
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{
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int i;
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struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
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for (i = 0; i < len; i++)
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write_data_reg(nand, buf[i]);
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}
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static int nuc900_check_rb(struct nuc900_nand *nand)
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{
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unsigned int val;
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spin_lock(&nand->lock);
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val = __raw_readl(nand->reg + REG_SMISR);
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val &= READYBUSY;
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spin_unlock(&nand->lock);
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return val;
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}
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static int nuc900_nand_devready(struct nand_chip *chip)
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{
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struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
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int ready;
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ready = (nuc900_check_rb(nand)) ? 1 : 0;
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return ready;
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}
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static void nuc900_nand_command_lp(struct nand_chip *chip,
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unsigned int command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct nuc900_nand *nand = mtd_to_nuc900(mtd);
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if (command == NAND_CMD_READOOB) {
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column += mtd->writesize;
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command = NAND_CMD_READ0;
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}
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write_cmd_reg(nand, command & 0xff);
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if (column != -1 || page_addr != -1) {
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if (column != -1) {
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if (chip->options & NAND_BUSWIDTH_16 &&
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!nand_opcode_8bits(command))
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column >>= 1;
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write_addr_reg(nand, column);
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write_addr_reg(nand, column >> 8 | ENDADDR);
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}
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if (page_addr != -1) {
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write_addr_reg(nand, page_addr);
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if (chip->options & NAND_ROW_ADDR_3) {
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write_addr_reg(nand, page_addr >> 8);
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write_addr_reg(nand, page_addr >> 16 | ENDADDR);
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} else {
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write_addr_reg(nand, page_addr >> 8 | ENDADDR);
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}
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}
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}
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switch (command) {
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case NAND_CMD_CACHEDPROG:
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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if (chip->legacy.dev_ready)
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break;
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udelay(chip->legacy.chip_delay);
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write_cmd_reg(nand, NAND_CMD_STATUS);
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write_cmd_reg(nand, command);
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while (!nuc900_check_rb(nand))
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;
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return;
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case NAND_CMD_RNDOUT:
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write_cmd_reg(nand, NAND_CMD_RNDOUTSTART);
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return;
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case NAND_CMD_READ0:
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write_cmd_reg(nand, NAND_CMD_READSTART);
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/* fall through */
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default:
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if (!chip->legacy.dev_ready) {
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udelay(chip->legacy.chip_delay);
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return;
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}
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}
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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ndelay(100);
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while (!chip->legacy.dev_ready(chip))
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;
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}
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static void nuc900_nand_enable(struct nuc900_nand *nand)
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{
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unsigned int val;
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spin_lock(&nand->lock);
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__raw_writel(RESET_FMI, (nand->reg + REG_FMICSR));
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val = __raw_readl(nand->reg + REG_FMICSR);
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if (!(val & NAND_EN))
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__raw_writel(val | NAND_EN, nand->reg + REG_FMICSR);
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val = __raw_readl(nand->reg + REG_SMCSR);
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val &= ~(SWRST|PSIZE|DMARWEN|BUSWID|ECC4EN|NANDCS);
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val |= WP;
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__raw_writel(val, nand->reg + REG_SMCSR);
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spin_unlock(&nand->lock);
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}
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static int nuc900_nand_probe(struct platform_device *pdev)
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{
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struct nuc900_nand *nuc900_nand;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct resource *res;
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nuc900_nand = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_nand),
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GFP_KERNEL);
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if (!nuc900_nand)
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return -ENOMEM;
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chip = &(nuc900_nand->chip);
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mtd = nand_to_mtd(chip);
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mtd->dev.parent = &pdev->dev;
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spin_lock_init(&nuc900_nand->lock);
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nuc900_nand->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(nuc900_nand->clk))
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return -ENOENT;
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clk_enable(nuc900_nand->clk);
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chip->legacy.cmdfunc = nuc900_nand_command_lp;
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chip->legacy.dev_ready = nuc900_nand_devready;
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chip->legacy.read_byte = nuc900_nand_read_byte;
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chip->legacy.write_buf = nuc900_nand_write_buf;
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chip->legacy.read_buf = nuc900_nand_read_buf;
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chip->legacy.chip_delay = 50;
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chip->options = 0;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->ecc.algo = NAND_ECC_HAMMING;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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nuc900_nand->reg = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(nuc900_nand->reg))
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return PTR_ERR(nuc900_nand->reg);
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nuc900_nand_enable(nuc900_nand);
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if (nand_scan(chip, 1))
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return -ENXIO;
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mtd_device_register(mtd, partitions, ARRAY_SIZE(partitions));
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platform_set_drvdata(pdev, nuc900_nand);
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return 0;
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}
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static int nuc900_nand_remove(struct platform_device *pdev)
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{
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struct nuc900_nand *nuc900_nand = platform_get_drvdata(pdev);
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nand_release(&nuc900_nand->chip);
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clk_disable(nuc900_nand->clk);
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return 0;
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}
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static struct platform_driver nuc900_nand_driver = {
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.probe = nuc900_nand_probe,
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.remove = nuc900_nand_remove,
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.driver = {
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.name = "nuc900-fmi",
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},
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};
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module_platform_driver(nuc900_nand_driver);
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MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
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MODULE_DESCRIPTION("w90p910/NUC9xx nand driver!");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:nuc900-fmi");
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