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cebe7373a7
This patch adds support to handle multiple instances of the TMU controllers. This is done by removing the static structure to register with the core thermal and creating it dynamically for each instance of the TMU controller. The interrupt is made shared type to handle shared interrupts. Now since the ISR needs the core thermal framework to be registered so request_irq is moved after the core registration is done. Also the identifier of the TMU controller is extracted from device tree alias. This will be used for TMU specific initialisation. Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
174 lines
5.7 KiB
C
174 lines
5.7 KiB
C
/*
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* exynos_tmu_data.c - Samsung EXYNOS tmu data file
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*
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* Copyright (C) 2013 Samsung Electronics
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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#include "exynos_tmu_data.h"
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#if defined(CONFIG_CPU_EXYNOS4210)
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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};
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struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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.tmu_data = {
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{
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.threshold = 80,
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.trigger_levels[0] = 5,
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.trigger_levels[1] = 20,
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.trigger_levels[2] = 30,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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.trigger_enable[3] = false,
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.max_trigger_level = 4,
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.gain = 15,
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.reference_voltage = 7,
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.cal_type = TYPE_ONE_POINT_TRIMMING,
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.min_efuse_value = 40,
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.max_efuse_value = 100,
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.first_point_trim = 25,
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.second_point_trim = 85,
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.default_temp_offset = 50,
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.freq_tab[0] = {
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.freq_clip_max = 800 * 1000,
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.temp_level = 85,
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},
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.freq_tab[1] = {
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.freq_clip_max = 200 * 1000,
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.temp_level = 100,
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},
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.freq_tab_count = 2,
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.type = SOC_ARCH_EXYNOS4210,
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.registers = &exynos4210_tmu_registers,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
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static const struct exynos_tmu_registers exynos5250_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
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.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
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.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.emul_con = EXYNOS_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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#define EXYNOS5250_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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.trigger_levels[1] = 103, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50, \
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.freq_tab[0] = { \
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.freq_clip_max = 800 * 1000, \
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.temp_level = 85, \
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}, \
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.freq_tab[1] = { \
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.freq_clip_max = 200 * 1000, \
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.temp_level = 103, \
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}, \
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.freq_tab_count = 2, \
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.type = SOC_ARCH_EXYNOS, \
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.registers = &exynos5250_tmu_registers,
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struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5250_TMU_DATA },
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},
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.tmu_count = 1,
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};
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#endif
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