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acd9e20cd9
Propagate sNaN payload in quieting in the legacy-NaN mode as well. If clearing the quiet bit would produce infinity, then set the next lower trailing significand field bit, matching the SB-1 and BMIPS5000 hardware implementations. Some other MIPS FPU hardware implementations do produce the default qNaN bit pattern instead. This reverts some changes made for semantics preservation with commit dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently bringing back most of the semantics from before commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced in the infinity case. Previously the default qNaN bit pattern was produced in that case. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
210 lines
4.8 KiB
C
210 lines
4.8 KiB
C
/* IEEE754 floating point arithmetic
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* double precision: common utilities
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*/
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/*
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* MIPS floating point support
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* Copyright (C) 1994-2000 Algorithmics Ltd.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/compiler.h>
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#include "ieee754dp.h"
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int ieee754dp_class(union ieee754dp x)
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{
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COMPXDP;
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EXPLODEXDP;
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return xc;
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}
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static inline int ieee754dp_isnan(union ieee754dp x)
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{
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return ieee754_class_nan(ieee754dp_class(x));
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}
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static inline int ieee754dp_issnan(union ieee754dp x)
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{
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int qbit;
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assert(ieee754dp_isnan(x));
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qbit = (DPMANT(x) & DP_MBIT(DP_FBITS - 1)) == DP_MBIT(DP_FBITS - 1);
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return ieee754_csr.nan2008 ^ qbit;
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}
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/*
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* Raise the Invalid Operation IEEE 754 exception
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* and convert the signaling NaN supplied to a quiet NaN.
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*/
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union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r)
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{
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assert(ieee754dp_issnan(r));
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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if (ieee754_csr.nan2008) {
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DPMANT(r) |= DP_MBIT(DP_FBITS - 1);
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} else {
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DPMANT(r) &= ~DP_MBIT(DP_FBITS - 1);
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if (!ieee754dp_isnan(r))
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DPMANT(r) |= DP_MBIT(DP_FBITS - 2);
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}
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return r;
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}
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static u64 ieee754dp_get_rounding(int sn, u64 xm)
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{
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/* inexact must round of 3 bits
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*/
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if (xm & (DP_MBIT(3) - 1)) {
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switch (ieee754_csr.rm) {
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case FPU_CSR_RZ:
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break;
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case FPU_CSR_RN:
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xm += 0x3 + ((xm >> 3) & 1);
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/* xm += (xm&0x8)?0x4:0x3 */
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break;
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case FPU_CSR_RU: /* toward +Infinity */
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if (!sn) /* ?? */
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xm += 0x8;
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break;
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case FPU_CSR_RD: /* toward -Infinity */
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if (sn) /* ?? */
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xm += 0x8;
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break;
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}
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}
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return xm;
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}
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/* generate a normal/denormal number with over,under handling
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* sn is sign
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* xe is an unbiased exponent
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* xm is 3bit extended precision value.
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*/
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union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
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{
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assert(xm); /* we don't gen exact zeros (probably should) */
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assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */
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assert(xm & (DP_HIDDEN_BIT << 3));
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if (xe < DP_EMIN) {
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/* strip lower bits */
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int es = DP_EMIN - xe;
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if (ieee754_csr.nod) {
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ieee754_setcx(IEEE754_UNDERFLOW);
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ieee754_setcx(IEEE754_INEXACT);
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switch(ieee754_csr.rm) {
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case FPU_CSR_RN:
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case FPU_CSR_RZ:
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return ieee754dp_zero(sn);
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case FPU_CSR_RU: /* toward +Infinity */
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if (sn == 0)
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return ieee754dp_min(0);
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else
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return ieee754dp_zero(1);
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case FPU_CSR_RD: /* toward -Infinity */
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if (sn == 0)
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return ieee754dp_zero(0);
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else
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return ieee754dp_min(1);
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}
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}
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if (xe == DP_EMIN - 1 &&
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ieee754dp_get_rounding(sn, xm) >> (DP_FBITS + 1 + 3))
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{
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/* Not tiny after rounding */
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ieee754_setcx(IEEE754_INEXACT);
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xm = ieee754dp_get_rounding(sn, xm);
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xm >>= 1;
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/* Clear grs bits */
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xm &= ~(DP_MBIT(3) - 1);
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xe++;
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}
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else {
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/* sticky right shift es bits
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*/
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xm = XDPSRS(xm, es);
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xe += es;
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assert((xm & (DP_HIDDEN_BIT << 3)) == 0);
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assert(xe == DP_EMIN);
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}
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}
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if (xm & (DP_MBIT(3) - 1)) {
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ieee754_setcx(IEEE754_INEXACT);
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if ((xm & (DP_HIDDEN_BIT << 3)) == 0) {
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ieee754_setcx(IEEE754_UNDERFLOW);
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}
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/* inexact must round of 3 bits
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*/
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xm = ieee754dp_get_rounding(sn, xm);
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/* adjust exponent for rounding add overflowing
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*/
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if (xm >> (DP_FBITS + 3 + 1)) {
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/* add causes mantissa overflow */
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xm >>= 1;
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xe++;
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}
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}
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/* strip grs bits */
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xm >>= 3;
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assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
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assert(xe >= DP_EMIN);
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if (xe > DP_EMAX) {
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ieee754_setcx(IEEE754_OVERFLOW);
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ieee754_setcx(IEEE754_INEXACT);
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/* -O can be table indexed by (rm,sn) */
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switch (ieee754_csr.rm) {
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case FPU_CSR_RN:
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return ieee754dp_inf(sn);
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case FPU_CSR_RZ:
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return ieee754dp_max(sn);
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case FPU_CSR_RU: /* toward +Infinity */
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if (sn == 0)
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return ieee754dp_inf(0);
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else
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return ieee754dp_max(1);
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case FPU_CSR_RD: /* toward -Infinity */
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if (sn == 0)
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return ieee754dp_max(0);
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else
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return ieee754dp_inf(1);
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}
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}
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/* gen norm/denorm/zero */
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if ((xm & DP_HIDDEN_BIT) == 0) {
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/* we underflow (tiny/zero) */
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assert(xe == DP_EMIN);
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if (ieee754_csr.mx & IEEE754_UNDERFLOW)
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ieee754_setcx(IEEE754_UNDERFLOW);
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return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm);
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} else {
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assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
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assert(xm & DP_HIDDEN_BIT);
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return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT);
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}
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}
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