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892204e06c
These are the main MIPS changes for 4.15. Fixes: - ralink: Fix MT7620 PCI build issues (4.5) - Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP (4.1) - Fix MIPS64 FP save/restore on 32-bit kernels (4.0) - ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19) - ralink: Fix MT7628 pinmux (3.19) - BCM47XX: Fix LED inversion on WRT54GSv1 (3.17) - Fix n32 core dumping as o32 since regset support (3.13) - ralink: Drop obsolete USB_ARCH_HAS_HCD select Build system: - Default to "generic" (multiplatform) system type instead of IP22 - Use generic little endian MIPS32 r2 configuration as default defconfig instead of ip22_defconfig FPU emulation: - Fix exception generation for certain R6 FPU instructions SMP: - Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id spaces Miscellaneous: - Add iomem resource for kernel bss section for kexec/kdump - Atomics: Nudge writes on bit unlock - DT files: Standardise "ok" -> "okay" Platform support: BMIPS: - Enable HARDIRQS_SW_RESEND Broadcom BCM63XX: - Add clkdev lookup support - Update clk driver, UART driver, DTs to handle named refclk from DTs - Split apart various clocks to more closely match hardware - Add ethernet clocks Cavium Octeon: - Remove usage of cvmx_wait() in favour of __delay() ImgTec Pistachio: - DT: Drop deprecated dwmmc num-slots property Ingenic JZ4780: - Add NFS root to Ci20 defconfig - Add watchdog to Ci20 DT & defconfig, and allow building of watchdog driver with this SoC Generic (multiplatform): - Migrate xilfpga (MIPSfpga) platform to the generic platform Lantiq xway: - Fix ASC0/ASC1 clocks Minor cleanups: - Define virt_to_pfn() - Make thread_saved_pc static - Simplify 32-bit sign extension in __read_64bit_c0_split() - DMA: Use vma_pages() helper - FPU emulation: Replace unsigned with unsigned int - MM: Removed unused lastpfn - Alchemy: Make clk_ops const - Lasat: Use setup_timer() helper - ralink: Use BIT() in MT7620 PCI driver -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAloJ8ecACgkQbAtpk944 dnqF3w/+IPcxcYl7QpVFvM3MsDgxJI8ENIkY5ffMi1UVM8gApAHuFSnGotikS8C8 jjnFyorrOkUKuuX9m9pfwfmvMHAy8j77so7kp2vpGjihe4iFntYJxJYUpYq8Ru8M jNzikrPbFv6eQyjwFEGuqxrJmsgTlJGiWA04a33LCfiFz5RZUSloHfPkjWiyWM1s xrbkbZpwvyX3jw39vguZvz5qjuUPViy/YOSyMhmTqnqDXqGmwlHgzev1/HEzISVe eN5n6bHGX5Dis4bCBPZuYbr6m96/z+xTKCKC7mlH0OnG/WWQtv9LFFU7o+ffRsI/ nPKEN/TFFA7V0b9zI/lxfVSoZ67IZa5TDA+PLnzX9UQAxOA/wgFHPOgqJZN3/BXo OBgTuguwq9D22uSrvrMoqmcU+zDXG4ZQQCgv7mUUw2E9gHnsYJykhVa4kQVj9MxE LkixhhE+Qabsh6L3wDtBntpgoOd58dxNiMJ7UAzDW3rmyjo+EEWN1eeCxQCrewlf 1aJaHeRoEOt/k7oPZWCd1InJ3vEsrNcO74KSZuQ+q0ytuqYOLUZ7ZXteA86VzroI 4qcftvR4cVOCz86B6NZdQQVOM95P7vgqBMJqh52i1pjQlVdvE92MBgzbm4BSOUAL Y+hybhhIwJriF8WtTq2goL8osvMODM1uM3Zlm0XtA5JfUYbWK/E= =xbL0 -----END PGP SIGNATURE----- Merge tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.15. Fixes: - ralink: Fix MT7620 PCI build issues (4.5) - Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP (4.1) - Fix MIPS64 FP save/restore on 32-bit kernels (4.0) - ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19) - ralink: Fix MT7628 pinmux (3.19) - BCM47XX: Fix LED inversion on WRT54GSv1 (3.17) - Fix n32 core dumping as o32 since regset support (3.13) - ralink: Drop obsolete USB_ARCH_HAS_HCD select Build system: - Default to "generic" (multiplatform) system type instead of IP22 - Use generic little endian MIPS32 r2 configuration as default defconfig instead of ip22_defconfig FPU emulation: - Fix exception generation for certain R6 FPU instructions SMP: - Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id spaces Miscellaneous: - Add iomem resource for kernel bss section for kexec/kdump - Atomics: Nudge writes on bit unlock - DT files: Standardise "ok" -> "okay" Minor cleanups: - Define virt_to_pfn() - Make thread_saved_pc static - Simplify 32-bit sign extension in __read_64bit_c0_split() - DMA: Use vma_pages() helper - FPU emulation: Replace unsigned with unsigned int - MM: Removed unused lastpfn - Alchemy: Make clk_ops const - Lasat: Use setup_timer() helper - ralink: Use BIT() in MT7620 PCI driver Platform support: BMIPS: - Enable HARDIRQS_SW_RESEND Broadcom BCM63XX: - Add clkdev lookup support - Update clk driver, UART driver, DTs to handle named refclk from DTs - Split apart various clocks to more closely match hardware - Add ethernet clocks Cavium Octeon: - Remove usage of cvmx_wait() in favour of __delay() ImgTec Pistachio: - DT: Drop deprecated dwmmc num-slots property Ingenic JZ4780: - Add NFS root to Ci20 defconfig - Add watchdog to Ci20 DT & defconfig, and allow building of watchdog driver with this SoC Generic (multiplatform): - Migrate xilfpga (MIPSfpga) platform to the generic platform Lantiq xway: - Fix ASC0/ASC1 clocks" * tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits) MIPS: Add iomem resource for kernel bss section. MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP MIPS: BMIPS: Enable HARDIRQS_SW_RESEND MIPS: pci: Make use of the BIT() macro inside the mt7620 driver MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver MIPS: pci: Remove duplicate define in mt7620 driver MIPS: ralink: Fix typo in mt7628 pinmux function MIPS: ralink: Fix MT7628 pinmux MIPS: Fix odd fp register warnings with MIPS64r2 watchdog: jz4780: Allow selection of jz4740-wdt driver MIPS/ptrace: Update syscall nr on register changes MIPS/ptrace: Pick up ptrace/seccomp changed syscalls MIPS: Fix an n32 core file generation regset support regression MIPS: Fix MIPS64 FP save/restore on 32-bit kernels MIPS: page.h: Define virt_to_pfn() MIPS: Xilfpga: Switch to using generic defconfigs MIPS: generic: Add support for MIPSfpga MIPS: Set defconfig target to a generic system for 32r2el MIPS: Kconfig: Set default MIPS system type as generic MIPS: DTS: Remove num-slots from Pistachio SoC ...
702 lines
16 KiB
C
702 lines
16 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/export.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/sched/mm.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/ftrace.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/idle.h>
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#include <asm/r4k-timer.h>
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#include <asm/mips-cps.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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#include <asm/maar.h>
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int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
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EXPORT_SYMBOL(__cpu_number_map);
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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EXPORT_SYMBOL(__cpu_logical_map);
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/* Number of TCs (or siblings in Intel speak) per CPU core */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* representing the TCs (or siblings in Intel speak) of each logical CPU */
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* representing the core map of multi-core chips of each logical CPU */
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
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static DECLARE_COMPLETION(cpu_starting);
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static DECLARE_COMPLETION(cpu_running);
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/*
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* A logcal cpu mask containing only one VPE per core to
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* reduce the number of IPIs on large MT systems.
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*/
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cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_foreign_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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/* representing cpus for which core maps can be computed */
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static cpumask_t cpu_core_setup_map;
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cpumask_t cpu_coherent_mask;
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#ifdef CONFIG_GENERIC_IRQ_IPI
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static struct irq_desc *call_desc;
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static struct irq_desc *sched_desc;
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#endif
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu(i, &cpu_sibling_setup_map) {
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if (cpus_are_siblings(cpu, i)) {
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cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
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}
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}
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} else
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cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
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}
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static inline void set_cpu_core_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_core_setup_map);
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for_each_cpu(i, &cpu_core_setup_map) {
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if (cpu_data[cpu].package == cpu_data[i].package) {
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cpumask_set_cpu(i, &cpu_core_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_core_map[i]);
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}
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}
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}
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/*
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* Calculate a new cpu_foreign_map mask whenever a
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* new cpu appears or disappears.
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*/
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void calculate_cpu_foreign_map(void)
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{
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int i, k, core_present;
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cpumask_t temp_foreign_map;
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/* Re-calculate the mask */
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cpumask_clear(&temp_foreign_map);
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for_each_online_cpu(i) {
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core_present = 0;
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for_each_cpu(k, &temp_foreign_map)
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if (cpus_are_siblings(i, k))
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core_present = 1;
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if (!core_present)
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cpumask_set_cpu(i, &temp_foreign_map);
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}
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for_each_online_cpu(i)
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cpumask_andnot(&cpu_foreign_map[i],
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&temp_foreign_map, &cpu_sibling_map[i]);
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}
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const struct plat_smp_ops *mp_ops;
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EXPORT_SYMBOL(mp_ops);
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void register_smp_ops(const struct plat_smp_ops *ops)
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{
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if (mp_ops)
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printk(KERN_WARNING "Overriding previously set SMP ops\n");
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mp_ops = ops;
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}
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#ifdef CONFIG_GENERIC_IRQ_IPI
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void mips_smp_send_ipi_single(int cpu, unsigned int action)
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{
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mips_smp_send_ipi_mask(cpumask_of(cpu), action);
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}
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void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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unsigned long flags;
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unsigned int core;
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int cpu;
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local_irq_save(flags);
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switch (action) {
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case SMP_CALL_FUNCTION:
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__ipi_send_mask(call_desc, mask);
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break;
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case SMP_RESCHEDULE_YOURSELF:
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__ipi_send_mask(sched_desc, mask);
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break;
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default:
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BUG();
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}
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if (mips_cpc_present()) {
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for_each_cpu(cpu, mask) {
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if (cpus_are_siblings(cpu, smp_processor_id()))
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continue;
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core = cpu_core(&cpu_data[cpu]);
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while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
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mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
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mips_cpc_lock_other(core);
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write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
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mips_cpc_unlock_other();
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mips_cm_unlock_other();
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}
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}
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}
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local_irq_restore(flags);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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scheduler_ipi();
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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generic_smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI call"
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};
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static void smp_ipi_init_one(unsigned int virq,
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struct irqaction *action)
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{
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int ret;
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irq_set_handler(virq, handle_percpu_irq);
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ret = setup_irq(virq, action);
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BUG_ON(ret);
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}
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static unsigned int call_virq, sched_virq;
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int mips_smp_ipi_allocate(const struct cpumask *mask)
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{
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int virq;
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struct irq_domain *ipidomain;
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struct device_node *node;
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node = of_irq_find_parent(of_root);
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ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
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/*
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* Some platforms have half DT setup. So if we found irq node but
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* didn't find an ipidomain, try to search for one that is not in the
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* DT.
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*/
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if (node && !ipidomain)
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ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
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/*
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* There are systems which use IPI IRQ domains, but only have one
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* registered when some runtime condition is met. For example a Malta
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* kernel may include support for GIC & CPU interrupt controller IPI
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* IRQ domains, but if run on a system with no GIC & no MT ASE then
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* neither will be supported or registered.
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*
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* We only have a problem if we're actually using multiple CPUs so fail
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* loudly if that is the case. Otherwise simply return, skipping IPI
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* setup, if we're running with only a single CPU.
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*/
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if (!ipidomain) {
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BUG_ON(num_present_cpus() > 1);
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return 0;
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}
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virq = irq_reserve_ipi(ipidomain, mask);
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BUG_ON(!virq);
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if (!call_virq)
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call_virq = virq;
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virq = irq_reserve_ipi(ipidomain, mask);
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BUG_ON(!virq);
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if (!sched_virq)
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sched_virq = virq;
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if (irq_domain_is_ipi_per_cpu(ipidomain)) {
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int cpu;
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for_each_cpu(cpu, mask) {
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smp_ipi_init_one(call_virq + cpu, &irq_call);
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smp_ipi_init_one(sched_virq + cpu, &irq_resched);
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}
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} else {
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smp_ipi_init_one(call_virq, &irq_call);
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smp_ipi_init_one(sched_virq, &irq_resched);
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}
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return 0;
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}
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int mips_smp_ipi_free(const struct cpumask *mask)
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{
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struct irq_domain *ipidomain;
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struct device_node *node;
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node = of_irq_find_parent(of_root);
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ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
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/*
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* Some platforms have half DT setup. So if we found irq node but
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* didn't find an ipidomain, try to search for one that is not in the
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* DT.
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*/
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if (node && !ipidomain)
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ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
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BUG_ON(!ipidomain);
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if (irq_domain_is_ipi_per_cpu(ipidomain)) {
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int cpu;
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for_each_cpu(cpu, mask) {
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remove_irq(call_virq + cpu, &irq_call);
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remove_irq(sched_virq + cpu, &irq_resched);
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}
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}
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irq_destroy_ipi(call_virq, mask);
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irq_destroy_ipi(sched_virq, mask);
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return 0;
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}
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static int __init mips_smp_ipi_init(void)
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{
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if (num_possible_cpus() == 1)
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return 0;
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mips_smp_ipi_allocate(cpu_possible_mask);
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call_desc = irq_to_desc(call_virq);
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sched_desc = irq_to_desc(sched_virq);
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return 0;
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}
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early_initcall(mips_smp_ipi_init);
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#endif
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/*
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* First C code run on the secondary CPUs after being started up by
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* the master.
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*/
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asmlinkage void start_secondary(void)
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{
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unsigned int cpu;
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cpu_probe();
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per_cpu_trap_init(false);
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mips_clockevent_init();
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mp_ops->init_secondary();
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cpu_report();
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maar_init();
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/*
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* XXX parity protection should be folded in here when it's converted
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* to an option instead of something based on .cputype
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*/
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calibrate_delay();
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preempt_disable();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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cpumask_set_cpu(cpu, &cpu_coherent_mask);
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notify_cpu_starting(cpu);
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/* Notify boot CPU that we're starting & ready to sync counters */
|
|
complete(&cpu_starting);
|
|
|
|
synchronise_count_slave(cpu);
|
|
|
|
/* The CPU is running and counters synchronised, now mark it online */
|
|
set_cpu_online(cpu, true);
|
|
|
|
set_cpu_sibling_map(cpu);
|
|
set_cpu_core_map(cpu);
|
|
|
|
calculate_cpu_foreign_map();
|
|
|
|
/*
|
|
* Notify boot CPU that we're up & online and it can safely return
|
|
* from __cpu_up
|
|
*/
|
|
complete(&cpu_running);
|
|
|
|
/*
|
|
* irq will be enabled in ->smp_finish(), enabling it too early
|
|
* is dangerous.
|
|
*/
|
|
WARN_ON_ONCE(!irqs_disabled());
|
|
mp_ops->smp_finish();
|
|
|
|
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
|
|
}
|
|
|
|
static void stop_this_cpu(void *dummy)
|
|
{
|
|
/*
|
|
* Remove this CPU:
|
|
*/
|
|
|
|
set_cpu_online(smp_processor_id(), false);
|
|
calculate_cpu_foreign_map();
|
|
local_irq_disable();
|
|
while (1);
|
|
}
|
|
|
|
void smp_send_stop(void)
|
|
{
|
|
smp_call_function(stop_this_cpu, NULL, 0);
|
|
}
|
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
}
|
|
|
|
/* called from main before smp_init() */
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
init_new_context(current, &init_mm);
|
|
current_thread_info()->cpu = 0;
|
|
mp_ops->prepare_cpus(max_cpus);
|
|
set_cpu_sibling_map(0);
|
|
set_cpu_core_map(0);
|
|
calculate_cpu_foreign_map();
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
|
init_cpu_present(cpu_possible_mask);
|
|
#endif
|
|
cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
|
|
}
|
|
|
|
/* preload SMP state for boot cpu */
|
|
void smp_prepare_boot_cpu(void)
|
|
{
|
|
set_cpu_possible(0, true);
|
|
set_cpu_online(0, true);
|
|
}
|
|
|
|
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
|
|
{
|
|
int err;
|
|
|
|
err = mp_ops->boot_secondary(cpu, tidle);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Wait for CPU to start and be ready to sync counters */
|
|
if (!wait_for_completion_timeout(&cpu_starting,
|
|
msecs_to_jiffies(1000))) {
|
|
pr_crit("CPU%u: failed to start\n", cpu);
|
|
return -EIO;
|
|
}
|
|
|
|
synchronise_count_master(cpu);
|
|
|
|
/* Wait for CPU to finish startup & mark itself online before return */
|
|
wait_for_completion(&cpu_running);
|
|
return 0;
|
|
}
|
|
|
|
/* Not really SMP stuff ... */
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void flush_tlb_all_ipi(void *info)
|
|
{
|
|
local_flush_tlb_all();
|
|
}
|
|
|
|
void flush_tlb_all(void)
|
|
{
|
|
on_each_cpu(flush_tlb_all_ipi, NULL, 1);
|
|
}
|
|
|
|
static void flush_tlb_mm_ipi(void *mm)
|
|
{
|
|
local_flush_tlb_mm((struct mm_struct *)mm);
|
|
}
|
|
|
|
/*
|
|
* Special Variant of smp_call_function for use by TLB functions:
|
|
*
|
|
* o No return value
|
|
* o collapses to normal function call on UP kernels
|
|
* o collapses to normal function call on systems with a single shared
|
|
* primary cache.
|
|
*/
|
|
static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
|
|
{
|
|
smp_call_function(func, info, 1);
|
|
}
|
|
|
|
static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
|
|
{
|
|
preempt_disable();
|
|
|
|
smp_on_other_tlbs(func, info);
|
|
func(info);
|
|
|
|
preempt_enable();
|
|
}
|
|
|
|
/*
|
|
* The following tlb flush calls are invoked when old translations are
|
|
* being torn down, or pte attributes are changing. For single threaded
|
|
* address spaces, a new context is obtained on the current cpu, and tlb
|
|
* context on other cpus are invalidated to force a new context allocation
|
|
* at switch_mm time, should the mm ever be used on other cpus. For
|
|
* multithreaded address spaces, intercpu interrupts have to be sent.
|
|
* Another case where intercpu interrupts are required is when the target
|
|
* mm might be active on another cpu (eg debuggers doing the flushes on
|
|
* behalf of debugees, kswapd stealing pages from another process etc).
|
|
* Kanoj 07/00.
|
|
*/
|
|
|
|
void flush_tlb_mm(struct mm_struct *mm)
|
|
{
|
|
preempt_disable();
|
|
|
|
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
|
|
smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, mm))
|
|
cpu_context(cpu, mm) = 0;
|
|
}
|
|
}
|
|
local_flush_tlb_mm(mm);
|
|
|
|
preempt_enable();
|
|
}
|
|
|
|
struct flush_tlb_data {
|
|
struct vm_area_struct *vma;
|
|
unsigned long addr1;
|
|
unsigned long addr2;
|
|
};
|
|
|
|
static void flush_tlb_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
|
|
{
|
|
struct mm_struct *mm = vma->vm_mm;
|
|
|
|
preempt_disable();
|
|
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
|
|
} else {
|
|
unsigned int cpu;
|
|
int exec = vma->vm_flags & VM_EXEC;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
/*
|
|
* flush_cache_range() will only fully flush icache if
|
|
* the VMA is executable, otherwise we must invalidate
|
|
* ASID without it appearing to has_valid_asid() as if
|
|
* mm has been completely unused by that CPU.
|
|
*/
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, mm))
|
|
cpu_context(cpu, mm) = !exec;
|
|
}
|
|
}
|
|
local_flush_tlb_range(vma, start, end);
|
|
preempt_enable();
|
|
}
|
|
|
|
static void flush_tlb_kernel_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
|
{
|
|
struct flush_tlb_data fd = {
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
|
|
}
|
|
|
|
static void flush_tlb_page_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_page(fd->vma, fd->addr1);
|
|
}
|
|
|
|
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
|
|
{
|
|
preempt_disable();
|
|
if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = page,
|
|
};
|
|
|
|
smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
/*
|
|
* flush_cache_page() only does partial flushes, so
|
|
* invalidate ASID without it appearing to
|
|
* has_valid_asid() as if mm has been completely unused
|
|
* by that CPU.
|
|
*/
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
|
|
cpu_context(cpu, vma->vm_mm) = 1;
|
|
}
|
|
}
|
|
local_flush_tlb_page(vma, page);
|
|
preempt_enable();
|
|
}
|
|
|
|
static void flush_tlb_one_ipi(void *info)
|
|
{
|
|
unsigned long vaddr = (unsigned long) info;
|
|
|
|
local_flush_tlb_one(vaddr);
|
|
}
|
|
|
|
void flush_tlb_one(unsigned long vaddr)
|
|
{
|
|
smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_tlb_page);
|
|
EXPORT_SYMBOL(flush_tlb_one);
|
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
|
|
static DEFINE_PER_CPU(call_single_data_t, tick_broadcast_csd);
|
|
|
|
void tick_broadcast(const struct cpumask *mask)
|
|
{
|
|
atomic_t *count;
|
|
call_single_data_t *csd;
|
|
int cpu;
|
|
|
|
for_each_cpu(cpu, mask) {
|
|
count = &per_cpu(tick_broadcast_count, cpu);
|
|
csd = &per_cpu(tick_broadcast_csd, cpu);
|
|
|
|
if (atomic_inc_return(count) == 1)
|
|
smp_call_function_single_async(cpu, csd);
|
|
}
|
|
}
|
|
|
|
static void tick_broadcast_callee(void *info)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
tick_receive_broadcast();
|
|
atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
|
|
}
|
|
|
|
static int __init tick_broadcast_init(void)
|
|
{
|
|
call_single_data_t *csd;
|
|
int cpu;
|
|
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++) {
|
|
csd = &per_cpu(tick_broadcast_csd, cpu);
|
|
csd->func = tick_broadcast_callee;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(tick_broadcast_init);
|
|
|
|
#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */
|