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fb615d61b5
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who: - Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year. - Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list. - Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej). - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself. New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead. Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
225 lines
5.4 KiB
C
225 lines
5.4 KiB
C
/*
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* Copyright (C) 2016 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define pr_fmt(fmt) "sead3: " fmt
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#include <linux/errno.h>
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#include <linux/libfdt.h>
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#include <linux/printk.h>
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#include <linux/sizes.h>
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#include <asm/fw/fw.h>
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#include <asm/io.h>
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#include <asm/machine.h>
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#include <asm/yamon-dt.h>
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#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
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#define SEAD_CONFIG_GIC_PRESENT BIT(1)
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#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
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#define MIPS_REVISION_MACHINE (0xf << 4)
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#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
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/*
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* Maximum 384MB RAM at physical address 0, preceding any I/O.
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*/
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static struct yamon_mem_region mem_regions[] __initdata = {
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/* start size */
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{ 0, SZ_256M + SZ_128M },
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{}
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};
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static __init bool sead3_detect(void)
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{
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uint32_t rev;
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rev = __raw_readl((void *)MIPS_REVISION);
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return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
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}
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static __init int append_memory(void *fdt)
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{
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return yamon_dt_append_memory(fdt, mem_regions);
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}
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static __init int remove_gic(void *fdt)
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{
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const unsigned int cpu_ehci_int = 2;
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const unsigned int cpu_uart_int = 4;
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const unsigned int cpu_eth_int = 6;
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int gic_off, cpu_off, uart_off, eth_off, ehci_off, err;
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uint32_t cfg, cpu_phandle;
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/* leave the GIC node intact if a GIC is present */
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cfg = __raw_readl((uint32_t *)SEAD_CONFIG);
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if (cfg & SEAD_CONFIG_GIC_PRESENT)
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return 0;
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gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
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if (gic_off < 0) {
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pr_err("unable to find DT GIC node: %d\n", gic_off);
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return gic_off;
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}
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err = fdt_nop_node(fdt, gic_off);
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if (err) {
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pr_err("unable to nop GIC node\n");
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return err;
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}
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cpu_off = fdt_node_offset_by_compatible(fdt, -1,
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"mti,cpu-interrupt-controller");
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if (cpu_off < 0) {
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pr_err("unable to find CPU intc node: %d\n", cpu_off);
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return cpu_off;
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}
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cpu_phandle = fdt_get_phandle(fdt, cpu_off);
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if (!cpu_phandle) {
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pr_err("unable to get CPU intc phandle\n");
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return -EINVAL;
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}
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uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
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while (uart_off >= 0) {
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err = fdt_setprop_u32(fdt, uart_off, "interrupt-parent",
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cpu_phandle);
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if (err) {
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pr_warn("unable to set UART interrupt-parent: %d\n",
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err);
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return err;
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}
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err = fdt_setprop_u32(fdt, uart_off, "interrupts",
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cpu_uart_int);
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if (err) {
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pr_err("unable to set UART interrupts property: %d\n",
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err);
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return err;
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}
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uart_off = fdt_node_offset_by_compatible(fdt, uart_off,
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"ns16550a");
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}
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if (uart_off != -FDT_ERR_NOTFOUND) {
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pr_err("error searching for UART DT node: %d\n", uart_off);
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return uart_off;
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}
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eth_off = fdt_node_offset_by_compatible(fdt, -1, "smsc,lan9115");
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if (eth_off < 0) {
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pr_err("unable to find ethernet DT node: %d\n", eth_off);
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return eth_off;
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}
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err = fdt_setprop_u32(fdt, eth_off, "interrupt-parent", cpu_phandle);
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if (err) {
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pr_err("unable to set ethernet interrupt-parent: %d\n", err);
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return err;
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}
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err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
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if (err) {
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pr_err("unable to set ethernet interrupts property: %d\n", err);
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return err;
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}
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ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
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if (ehci_off < 0) {
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pr_err("unable to find EHCI DT node: %d\n", ehci_off);
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return ehci_off;
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}
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err = fdt_setprop_u32(fdt, ehci_off, "interrupt-parent", cpu_phandle);
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if (err) {
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pr_err("unable to set EHCI interrupt-parent: %d\n", err);
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return err;
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}
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err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
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if (err) {
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pr_err("unable to set EHCI interrupts property: %d\n", err);
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return err;
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}
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return 0;
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}
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static const struct mips_fdt_fixup sead3_fdt_fixups[] __initconst = {
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{ yamon_dt_append_cmdline, "append command line" },
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{ append_memory, "append memory" },
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{ remove_gic, "remove GIC when not present" },
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{ yamon_dt_serial_config, "append serial configuration" },
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{ },
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};
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static __init const void *sead3_fixup_fdt(const void *fdt,
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const void *match_data)
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{
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static unsigned char fdt_buf[16 << 10] __initdata;
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int err;
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if (fdt_check_header(fdt))
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panic("Corrupt DT");
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/* if this isn't SEAD3, something went wrong */
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BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
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fw_init_cmdline();
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err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf),
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fdt, sead3_fdt_fixups);
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if (err)
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panic("Unable to fixup FDT: %d", err);
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return fdt_buf;
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}
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static __init unsigned int sead3_measure_hpt_freq(void)
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{
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void __iomem *status_reg = (void __iomem *)0xbf000410;
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unsigned int freq, orig, tick = 0;
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unsigned long flags;
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local_irq_save(flags);
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orig = readl(status_reg) & 0x2; /* get original sample */
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/* wait for transition */
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while ((readl(status_reg) & 0x2) == orig)
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;
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orig = orig ^ 0x2; /* flip the bit */
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write_c0_count(0);
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/* wait 1 second (the sampling clock transitions every 10ms) */
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while (tick < 100) {
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/* wait for transition */
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while ((readl(status_reg) & 0x2) == orig)
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;
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orig = orig ^ 0x2; /* flip the bit */
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tick++;
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}
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freq = read_c0_count();
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local_irq_restore(flags);
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return freq;
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}
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extern char __dtb_sead3_begin[];
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MIPS_MACHINE(sead3) = {
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.fdt = __dtb_sead3_begin,
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.detect = sead3_detect,
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.fixup_fdt = sead3_fixup_fdt,
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.measure_hpt_freq = sead3_measure_hpt_freq,
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};
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