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760d969f9e
Removed wl1271_spi.h header as there's no more need to access functions declared there outside of wl1271_spi.c. Also made those SPI access functions static. Signed-off-by: Teemu Paasikivi <ext-teemu.3.paasikivi@nokia.com> Reviewed-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
171 lines
5.0 KiB
C
171 lines
5.0 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/crc7.h>
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#include <linux/spi/spi.h>
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#include "wl1271.h"
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#include "wl12xx_80211.h"
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#include "wl1271_io.h"
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#define OCP_CMD_LOOP 32
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#define OCP_CMD_WRITE 0x1
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#define OCP_CMD_READ 0x2
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#define OCP_READY_MASK BIT(18)
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#define OCP_STATUS_MASK (BIT(16) | BIT(17))
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#define OCP_STATUS_NO_RESP 0x00000
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#define OCP_STATUS_OK 0x10000
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#define OCP_STATUS_REQ_FAILED 0x20000
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#define OCP_STATUS_RESP_ERROR 0x30000
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void wl1271_disable_interrupts(struct wl1271 *wl)
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{
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wl->if_ops->disable_irq(wl);
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}
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void wl1271_enable_interrupts(struct wl1271 *wl)
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{
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wl->if_ops->enable_irq(wl);
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}
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/* Set the SPI partitions to access the chip addresses
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*
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* To simplify driver code, a fixed (virtual) memory map is defined for
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* register and memory addresses. Because in the chipset, in different stages
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* of operation, those addresses will move around, an address translation
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* mechanism is required.
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*
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* There are four partitions (three memory and one register partition),
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* which are mapped to two different areas of the hardware memory.
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*
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* Virtual address
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* space
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*
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* | |
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* ...+----+--> mem.start
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* Physical address ... | |
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* space ... | | [PART_0]
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* ... | |
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* 00000000 <--+----+... ...+----+--> mem.start + mem.size
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* | | ... | |
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* |MEM | ... | |
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* | | ... | |
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* mem.size <--+----+... | | {unused area)
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* | | ... | |
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* |REG | ... | |
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* mem.size | | ... | |
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* + <--+----+... ...+----+--> reg.start
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* reg.size | | ... | |
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* |MEM2| ... | | [PART_1]
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* | | ... | |
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* ...+----+--> reg.start + reg.size
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* | |
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*
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*/
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int wl1271_set_partition(struct wl1271 *wl,
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struct wl1271_partition_set *p)
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{
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/* copy partition info */
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memcpy(&wl->part, p, sizeof(*p));
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wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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p->mem.start, p->mem.size);
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wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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p->reg.start, p->reg.size);
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wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
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p->mem2.start, p->mem2.size);
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wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
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p->mem3.start, p->mem3.size);
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/* write partition info to the chipset */
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wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
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wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
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wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
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wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
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wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
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wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
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wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
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return 0;
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}
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void wl1271_io_reset(struct wl1271 *wl)
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{
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wl->if_ops->reset(wl);
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}
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void wl1271_io_init(struct wl1271 *wl)
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{
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wl->if_ops->init(wl);
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}
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void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
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{
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/* write address >> 1 + 0x30000 to OCP_POR_CTR */
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addr = (addr >> 1) + 0x30000;
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wl1271_write32(wl, OCP_POR_CTR, addr);
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/* write value to OCP_POR_WDATA */
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wl1271_write32(wl, OCP_DATA_WRITE, val);
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/* write 1 to OCP_CMD */
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wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
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}
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u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
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{
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u32 val;
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int timeout = OCP_CMD_LOOP;
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/* write address >> 1 + 0x30000 to OCP_POR_CTR */
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addr = (addr >> 1) + 0x30000;
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wl1271_write32(wl, OCP_POR_CTR, addr);
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/* write 2 to OCP_CMD */
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wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
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/* poll for data ready */
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do {
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val = wl1271_read32(wl, OCP_DATA_READ);
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} while (!(val & OCP_READY_MASK) && --timeout);
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if (!timeout) {
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wl1271_warning("Top register access timed out.");
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return 0xffff;
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}
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/* check data status and return if OK */
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if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
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return val & 0xffff;
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else {
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wl1271_warning("Top register access returned error.");
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return 0xffff;
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}
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}
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