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aa96a18d22
Add various functionality needed to enable a imx53 low power idle state. This includes adding the imx53 gpc_dvfs clock and making a common imx5_late_init function and initializing all imx53 MACHINE_STATE late_init calls to imx5_late_init. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
154 lines
4.9 KiB
C
154 lines
4.9 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <mach/common.h>
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#include <mach/mx53.h>
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/*
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* Lookup table for attaching a specific name and platform_data pointer to
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* devices as they get created by of_platform_populate(). Ideally this table
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* would not exist, but the current clock implementation depends on some devices
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* having a specific name.
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*/
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static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
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OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
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OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
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OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
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OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
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OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
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OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
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OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
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OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
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OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
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OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
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OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
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OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
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OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
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{ /* sentinel */ }
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};
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static int __init imx53_tzic_add_irq_domain(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
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return 0;
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}
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static int __init imx53_gpio_add_irq_domain(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
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gpio_irq_base -= 32;
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irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
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return 0;
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}
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static const struct of_device_id imx53_irq_match[] __initconst = {
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{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
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{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
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{ /* sentinel */ }
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};
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static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
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{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
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{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
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{ .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
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{ .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
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{ /* sentinel */ }
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};
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static void __init imx53_qsb_init(void)
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{
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struct clk *clk;
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clk = clk_get_sys(NULL, "ssi_ext1");
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if (IS_ERR(clk)) {
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pr_err("failed to get clk ssi_ext1\n");
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return;
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}
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clk_register_clkdev(clk, NULL, "0-000a");
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}
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static void __init imx53_dt_init(void)
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{
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struct device_node *node;
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const struct of_device_id *of_id;
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void (*func)(void);
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of_irq_init(imx53_irq_match);
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pinctrl_provide_dummies();
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node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
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if (node) {
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of_id = of_match_node(imx53_iomuxc_of_match, node);
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func = of_id->data;
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func();
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of_node_put(node);
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}
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if (of_machine_is_compatible("fsl,imx53-qsb"))
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imx53_qsb_init();
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of_platform_populate(NULL, of_default_bus_match_table,
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imx53_auxdata_lookup, NULL);
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}
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static void __init imx53_timer_init(void)
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{
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mx53_clocks_init_dt();
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}
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static struct sys_timer imx53_timer = {
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.init = imx53_timer_init,
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};
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static const char *imx53_dt_board_compat[] __initdata = {
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"fsl,imx53-ard",
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"fsl,imx53-evk",
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"fsl,imx53-qsb",
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"fsl,imx53-smd",
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"fsl,imx53",
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NULL
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};
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DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
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.map_io = mx53_map_io,
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.init_early = imx53_init_early,
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.init_irq = mx53_init_irq,
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.handle_irq = imx53_handle_irq,
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.timer = &imx53_timer,
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.init_machine = imx53_dt_init,
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.init_late = imx53_init_late,
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.dt_compat = imx53_dt_board_compat,
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.restart = mxc_restart,
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MACHINE_END
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