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393cae5f32
Start from ACE1.x, DOAISE is added to AC timing control register bit 5, it combines with DOAIS to get effective timing, and has the default value 1. The current code fills DOAIS, DACTQE and DODS bits to a variable initialized to zero, and updates the variable to AC timing control register. With this operation, We change DOAISE to 0, and force a much more aggressive timing. The timing is even unable to form a working waveform on SDA pin. This patch uses read-modify-write operation for the AC timing control register access, thus makes sure those bits not supposed and intended to change are not touched. Signed-off-by: Chao Song <chao.song@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20231127124735.2080562-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
678 lines
17 KiB
C
678 lines
17 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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// Copyright(c) 2023 Intel Corporation. All rights reserved.
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/*
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* Soundwire Intel ops for LunarLake
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*/
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#include <linux/acpi.h>
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#include <linux/device.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_intel.h>
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#include <sound/pcm_params.h>
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#include <sound/hda-mlink.h>
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#include "cadence_master.h"
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#include "bus.h"
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#include "intel.h"
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/*
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* shim vendor-specific (vs) ops
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*/
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static void intel_shim_vs_init(struct sdw_intel *sdw)
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{
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void __iomem *shim_vs = sdw->link_res->shim_vs;
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u16 act;
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act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);
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u16p_replace_bits(&act, 0x1, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
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act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE;
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act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DODS;
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intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act);
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usleep_range(10, 15);
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}
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static int intel_shim_check_wake(struct sdw_intel *sdw)
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{
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void __iomem *shim_vs;
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u16 wake_sts;
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shim_vs = sdw->link_res->shim_vs;
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wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS);
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return wake_sts & SDW_SHIM2_INTEL_VS_WAKEEN_PWS;
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}
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static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
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{
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void __iomem *shim_vs = sdw->link_res->shim_vs;
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u16 wake_en;
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u16 wake_sts;
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wake_en = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN);
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if (wake_enable) {
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/* Enable the wakeup */
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wake_en |= SDW_SHIM2_INTEL_VS_WAKEEN_PWE;
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intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en);
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} else {
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/* Disable the wake up interrupt */
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wake_en &= ~SDW_SHIM2_INTEL_VS_WAKEEN_PWE;
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intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en);
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/* Clear wake status (W1C) */
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wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS);
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wake_sts |= SDW_SHIM2_INTEL_VS_WAKEEN_PWS;
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intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS, wake_sts);
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}
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}
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static int intel_link_power_up(struct sdw_intel *sdw)
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{
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struct sdw_bus *bus = &sdw->cdns.bus;
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struct sdw_master_prop *prop = &bus->prop;
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u32 *shim_mask = sdw->link_res->shim_mask;
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unsigned int link_id = sdw->instance;
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u32 syncprd;
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int ret;
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mutex_lock(sdw->link_res->shim_lock);
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if (!*shim_mask) {
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/* we first need to program the SyncPRD/CPU registers */
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dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
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if (prop->mclk_freq % 6000000)
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syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
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else
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syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
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ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd);
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if (ret < 0) {
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dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n",
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__func__, ret);
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goto out;
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}
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}
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ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id);
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if (ret < 0) {
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dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n",
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__func__, ret);
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goto out;
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}
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if (!*shim_mask) {
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/* SYNCPU will change once link is active */
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ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus);
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if (ret < 0) {
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dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n",
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__func__, ret);
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goto out;
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}
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}
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*shim_mask |= BIT(link_id);
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sdw->cdns.link_up = true;
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intel_shim_vs_init(sdw);
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out:
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mutex_unlock(sdw->link_res->shim_lock);
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return ret;
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}
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static int intel_link_power_down(struct sdw_intel *sdw)
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{
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u32 *shim_mask = sdw->link_res->shim_mask;
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unsigned int link_id = sdw->instance;
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int ret;
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mutex_lock(sdw->link_res->shim_lock);
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sdw->cdns.link_up = false;
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*shim_mask &= ~BIT(link_id);
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ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id);
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if (ret < 0) {
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dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n",
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__func__, ret);
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/*
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* we leave the sdw->cdns.link_up flag as false since we've disabled
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* the link at this point and cannot handle interrupts any longer.
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*/
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}
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mutex_unlock(sdw->link_res->shim_lock);
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return ret;
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}
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static void intel_sync_arm(struct sdw_intel *sdw)
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{
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unsigned int link_id = sdw->instance;
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mutex_lock(sdw->link_res->shim_lock);
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hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id);
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mutex_unlock(sdw->link_res->shim_lock);
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}
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static int intel_sync_go_unlocked(struct sdw_intel *sdw)
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{
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int ret;
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ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus);
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if (ret < 0)
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dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret);
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return ret;
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}
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static int intel_sync_go(struct sdw_intel *sdw)
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{
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int ret;
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mutex_lock(sdw->link_res->shim_lock);
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ret = intel_sync_go_unlocked(sdw);
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mutex_unlock(sdw->link_res->shim_lock);
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return ret;
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}
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static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw)
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{
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return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus);
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}
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/* DAI callbacks */
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static int intel_params_stream(struct sdw_intel *sdw,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai,
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struct snd_pcm_hw_params *hw_params,
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int link_id, int alh_stream_id)
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{
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struct sdw_intel_link_res *res = sdw->link_res;
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struct sdw_intel_stream_params_data params_data;
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params_data.substream = substream;
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params_data.dai = dai;
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params_data.hw_params = hw_params;
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params_data.link_id = link_id;
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params_data.alh_stream_id = alh_stream_id;
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if (res->ops && res->ops->params_stream && res->dev)
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return res->ops->params_stream(res->dev,
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¶ms_data);
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return -EIO;
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}
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static int intel_free_stream(struct sdw_intel *sdw,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai,
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int link_id)
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{
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struct sdw_intel_link_res *res = sdw->link_res;
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struct sdw_intel_stream_free_data free_data;
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free_data.substream = substream;
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free_data.dai = dai;
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free_data.link_id = link_id;
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if (res->ops && res->ops->free_stream && res->dev)
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return res->ops->free_stream(res->dev,
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&free_data);
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return 0;
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}
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/*
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* DAI operations
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*/
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static int intel_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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struct sdw_cdns_dai_runtime *dai_runtime;
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struct sdw_cdns_pdi *pdi;
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struct sdw_stream_config sconfig;
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struct sdw_port_config *pconfig;
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int ch, dir;
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int ret;
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dai_runtime = cdns->dai_runtime_array[dai->id];
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if (!dai_runtime)
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return -EIO;
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ch = params_channels(params);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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dir = SDW_DATA_DIR_RX;
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else
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dir = SDW_DATA_DIR_TX;
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pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
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if (!pdi) {
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ret = -EINVAL;
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goto error;
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}
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/* the SHIM will be configured in the callback functions */
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sdw_cdns_config_stream(cdns, ch, dir, pdi);
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/* store pdi and state, may be needed in prepare step */
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dai_runtime->paused = false;
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dai_runtime->suspended = false;
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dai_runtime->pdi = pdi;
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/* Inform DSP about PDI stream number */
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ret = intel_params_stream(sdw, substream, dai, params,
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sdw->instance,
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pdi->intel_alh_id);
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if (ret)
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goto error;
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sconfig.direction = dir;
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sconfig.ch_count = ch;
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sconfig.frame_rate = params_rate(params);
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sconfig.type = dai_runtime->stream_type;
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sconfig.bps = snd_pcm_format_width(params_format(params));
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/* Port configuration */
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pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
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if (!pconfig) {
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ret = -ENOMEM;
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goto error;
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}
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pconfig->num = pdi->num;
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pconfig->ch_mask = (1 << ch) - 1;
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ret = sdw_stream_add_master(&cdns->bus, &sconfig,
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pconfig, 1, dai_runtime->stream);
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if (ret)
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dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
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kfree(pconfig);
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error:
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return ret;
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}
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static int intel_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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struct sdw_cdns_dai_runtime *dai_runtime;
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int ch, dir;
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int ret = 0;
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dai_runtime = cdns->dai_runtime_array[dai->id];
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if (!dai_runtime) {
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dev_err(dai->dev, "failed to get dai runtime in %s\n",
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__func__);
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return -EIO;
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}
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if (dai_runtime->suspended) {
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struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
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struct snd_pcm_hw_params *hw_params;
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hw_params = &rtd->dpcm[substream->stream].hw_params;
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dai_runtime->suspended = false;
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/*
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* .prepare() is called after system resume, where we
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* need to reinitialize the SHIM/ALH/Cadence IP.
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* .prepare() is also called to deal with underflows,
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* but in those cases we cannot touch ALH/SHIM
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* registers
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*/
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/* configure stream */
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ch = params_channels(hw_params);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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dir = SDW_DATA_DIR_RX;
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else
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dir = SDW_DATA_DIR_TX;
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/* the SHIM will be configured in the callback functions */
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sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi);
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/* Inform DSP about PDI stream number */
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ret = intel_params_stream(sdw, substream, dai,
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hw_params,
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sdw->instance,
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dai_runtime->pdi->intel_alh_id);
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}
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return ret;
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}
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static int
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intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
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{
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struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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struct sdw_cdns_dai_runtime *dai_runtime;
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int ret;
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dai_runtime = cdns->dai_runtime_array[dai->id];
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if (!dai_runtime)
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return -EIO;
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/*
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* The sdw stream state will transition to RELEASED when stream->
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* master_list is empty. So the stream state will transition to
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* DEPREPARED for the first cpu-dai and to RELEASED for the last
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* cpu-dai.
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*/
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ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream);
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if (ret < 0) {
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dev_err(dai->dev, "remove master from stream %s failed: %d\n",
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dai_runtime->stream->name, ret);
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return ret;
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}
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ret = intel_free_stream(sdw, substream, dai, sdw->instance);
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if (ret < 0) {
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dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
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return ret;
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}
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dai_runtime->pdi = NULL;
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return 0;
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}
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static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
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void *stream, int direction)
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{
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return cdns_set_sdw_stream(dai, stream, direction);
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}
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static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
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int direction)
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{
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struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
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struct sdw_cdns_dai_runtime *dai_runtime;
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dai_runtime = cdns->dai_runtime_array[dai->id];
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if (!dai_runtime)
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return ERR_PTR(-EINVAL);
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return dai_runtime->stream;
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}
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static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
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{
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struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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struct sdw_intel_link_res *res = sdw->link_res;
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struct sdw_cdns_dai_runtime *dai_runtime;
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int ret = 0;
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/*
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* The .trigger callback is used to program HDaudio DMA and send required IPC to audio
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* firmware.
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*/
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if (res->ops && res->ops->trigger) {
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ret = res->ops->trigger(substream, cmd, dai);
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if (ret < 0)
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return ret;
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}
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dai_runtime = cdns->dai_runtime_array[dai->id];
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if (!dai_runtime) {
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dev_err(dai->dev, "failed to get dai runtime in %s\n",
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__func__);
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return -EIO;
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}
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_SUSPEND:
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/*
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* The .prepare callback is used to deal with xruns and resume operations.
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* In the case of xruns, the DMAs and SHIM registers cannot be touched,
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* but for resume operations the DMAs and SHIM registers need to be initialized.
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* the .trigger callback is used to track the suspend case only.
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*/
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dai_runtime->suspended = true;
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break;
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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dai_runtime->paused = true;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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dai_runtime->paused = false;
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break;
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default:
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break;
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}
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return ret;
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}
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static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
|
|
.hw_params = intel_hw_params,
|
|
.prepare = intel_prepare,
|
|
.hw_free = intel_hw_free,
|
|
.trigger = intel_trigger,
|
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.set_stream = intel_pcm_set_sdw_stream,
|
|
.get_stream = intel_get_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver dai_component = {
|
|
.name = "soundwire",
|
|
};
|
|
|
|
/*
|
|
* PDI routines
|
|
*/
|
|
static void intel_pdi_init(struct sdw_intel *sdw,
|
|
struct sdw_cdns_stream_config *config)
|
|
{
|
|
void __iomem *shim = sdw->link_res->shim;
|
|
int pcm_cap;
|
|
|
|
/* PCM Stream Capability */
|
|
pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP);
|
|
|
|
config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap);
|
|
config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
|
|
config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
|
|
|
|
dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
|
|
config->pcm_bd, config->pcm_in, config->pcm_out);
|
|
}
|
|
|
|
static int
|
|
intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
|
|
{
|
|
void __iomem *shim = sdw->link_res->shim;
|
|
|
|
/* zero based values for channel count in register */
|
|
return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1;
|
|
}
|
|
|
|
static void intel_pdi_get_ch_update(struct sdw_intel *sdw,
|
|
struct sdw_cdns_pdi *pdi,
|
|
unsigned int num_pdi,
|
|
unsigned int *num_ch)
|
|
{
|
|
int ch_count = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < num_pdi; i++) {
|
|
pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
|
|
ch_count += pdi->ch_count;
|
|
pdi++;
|
|
}
|
|
|
|
*num_ch = ch_count;
|
|
}
|
|
|
|
static void intel_pdi_stream_ch_update(struct sdw_intel *sdw,
|
|
struct sdw_cdns_streams *stream)
|
|
{
|
|
intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
|
|
&stream->num_ch_bd);
|
|
|
|
intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
|
|
&stream->num_ch_in);
|
|
|
|
intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
|
|
&stream->num_ch_out);
|
|
}
|
|
|
|
static int intel_create_dai(struct sdw_cdns *cdns,
|
|
struct snd_soc_dai_driver *dais,
|
|
enum intel_pdi_type type,
|
|
u32 num, u32 off, u32 max_ch)
|
|
{
|
|
int i;
|
|
|
|
if (!num)
|
|
return 0;
|
|
|
|
for (i = off; i < (off + num); i++) {
|
|
dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
|
|
"SDW%d Pin%d",
|
|
cdns->instance, i);
|
|
if (!dais[i].name)
|
|
return -ENOMEM;
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
|
|
dais[i].playback.channels_min = 1;
|
|
dais[i].playback.channels_max = max_ch;
|
|
}
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
|
|
dais[i].capture.channels_min = 1;
|
|
dais[i].capture.channels_max = max_ch;
|
|
}
|
|
|
|
dais[i].ops = &intel_pcm_dai_ops;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_register_dai(struct sdw_intel *sdw)
|
|
{
|
|
struct sdw_cdns_dai_runtime **dai_runtime_array;
|
|
struct sdw_cdns_stream_config config;
|
|
struct sdw_cdns *cdns = &sdw->cdns;
|
|
struct sdw_cdns_streams *stream;
|
|
struct snd_soc_dai_driver *dais;
|
|
int num_dai;
|
|
int ret;
|
|
int off = 0;
|
|
|
|
/* Read the PDI config and initialize cadence PDI */
|
|
intel_pdi_init(sdw, &config);
|
|
ret = sdw_cdns_pdi_init(cdns, config);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
|
|
|
|
/* DAIs are created based on total number of PDIs supported */
|
|
num_dai = cdns->pcm.num_pdi;
|
|
|
|
dai_runtime_array = devm_kcalloc(cdns->dev, num_dai,
|
|
sizeof(struct sdw_cdns_dai_runtime *),
|
|
GFP_KERNEL);
|
|
if (!dai_runtime_array)
|
|
return -ENOMEM;
|
|
cdns->dai_runtime_array = dai_runtime_array;
|
|
|
|
dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
|
|
if (!dais)
|
|
return -ENOMEM;
|
|
|
|
/* Create PCM DAIs */
|
|
stream = &cdns->pcm;
|
|
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
|
|
off, stream->num_ch_in);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_in;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
|
|
off, stream->num_ch_out);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_out;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
|
|
off, stream->num_ch_bd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_snd_soc_register_component(cdns->dev, &dai_component,
|
|
dais, num_dai);
|
|
}
|
|
|
|
static void intel_program_sdi(struct sdw_intel *sdw, int dev_num)
|
|
{
|
|
int ret;
|
|
|
|
ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num);
|
|
if (ret < 0)
|
|
dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n",
|
|
__func__, sdw->instance, dev_num);
|
|
}
|
|
|
|
const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = {
|
|
.debugfs_init = intel_ace2x_debugfs_init,
|
|
.debugfs_exit = intel_ace2x_debugfs_exit,
|
|
|
|
.register_dai = intel_register_dai,
|
|
|
|
.check_clock_stop = intel_check_clock_stop,
|
|
.start_bus = intel_start_bus,
|
|
.start_bus_after_reset = intel_start_bus_after_reset,
|
|
.start_bus_after_clock_stop = intel_start_bus_after_clock_stop,
|
|
.stop_bus = intel_stop_bus,
|
|
|
|
.link_power_up = intel_link_power_up,
|
|
.link_power_down = intel_link_power_down,
|
|
|
|
.shim_check_wake = intel_shim_check_wake,
|
|
.shim_wake = intel_shim_wake,
|
|
|
|
.pre_bank_switch = intel_pre_bank_switch,
|
|
.post_bank_switch = intel_post_bank_switch,
|
|
|
|
.sync_arm = intel_sync_arm,
|
|
.sync_go_unlocked = intel_sync_go_unlocked,
|
|
.sync_go = intel_sync_go,
|
|
.sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
|
|
|
|
.program_sdi = intel_program_sdi,
|
|
};
|
|
EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, SOUNDWIRE_INTEL);
|
|
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);
|