linux/arch/arm64/mm
Peter Maydell cc19846079 arm64: fault: Don't leak data in ESR context for user fault on kernel VA
If userspace faults on a kernel address, handing them the raw ESR
value on the sigframe as part of the delivered signal can leak data
useful to attackers who are using information about the underlying hardware
fault type (e.g. translation vs permission) as a mechanism to defeat KASLR.

However there are also legitimate uses for the information provided
in the ESR -- notably the GCC and LLVM sanitizers use this to report
whether wild pointer accesses by the application are reads or writes
(since a wild write is a more serious bug than a wild read), so we
don't want to drop the ESR information entirely.

For faulting addresses in the kernel, sanitize the ESR. We choose
to present userspace with the illusion that there is nothing mapped
in the kernel's part of the address space at all, by reporting all
faults as level 0 translation faults taken to EL1.

These fields are safe to pass through to userspace as they depend
only on the instruction that userspace used to provoke the fault:
 EC IL (always)
 ISV CM WNR (for all data aborts)
All the other fields in ESR except DFSC are architecturally RES0
for an L0 translation fault taken to EL1, so can be zeroed out
without confusing userspace.

The illusion is not entirely perfect, as there is a tiny wrinkle
where we will report an alignment fault that was not due to the memory
type (for instance a LDREX to an unaligned address) as a translation
fault, whereas if you do this on real unmapped memory the alignment
fault takes precedence. This is not likely to trip anybody up in
practice, as the only users we know of for the ESR information who
care about the behaviour for kernel addresses only really want to
know about the WnR bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-05-22 17:14:20 +01:00
..
cache.S arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC 2018-03-09 13:57:57 +00:00
context.c arm64: Move BP hardening to check_and_switch_context 2018-01-23 15:40:29 +00:00
copypage.c arm64: Defer dcache flush in __cpu_copy_user_page 2015-12-17 11:07:13 +00:00
dma-mapping.c Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)" 2018-03-27 12:04:51 +01:00
dump.c arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables 2018-02-16 18:13:57 +00:00
extable.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
fault.c arm64: fault: Don't leak data in ESR context for user fault on kernel VA 2018-05-22 17:14:20 +01:00
flush.c arm64: mm: drop addr parameter from sync icache and dcache 2018-04-24 09:23:00 +01:00
hugetlbpage.c arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables 2018-02-16 18:13:57 +00:00
init.c arm64: To remove initrd reserved area entry from memblock 2018-05-01 10:19:30 +01:00
ioremap.c arm64: use is_vmalloc_addr 2017-02-09 13:47:56 +00:00
kasan_init.c arm64: kasan: avoid pfn_to_nid() before page array is initialized 2018-04-17 16:16:59 +01:00
Makefile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
mmap.c exec: pass stack rlimit into mm layout functions 2018-04-11 10:28:37 -07:00
mmu.c mm/vmalloc: add interfaces to free unmapped page table 2018-03-22 17:07:01 -07:00
numa.c arm64/numa: Drop duplicate message 2017-07-20 17:03:53 +01:00
pageattr.c arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables 2018-02-16 18:13:57 +00:00
pgd.c arm64: handle 52-bit addresses in TTBR 2017-12-22 17:35:21 +00:00
physaddr.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
proc.S arm64: Delay enabling hardware DBM feature 2018-03-26 18:01:44 +01:00
ptdump_debugfs.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00