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65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2017 MediaTek Inc.
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* Author: Kevin Chen <kevin-cw.chen@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt6797-clk.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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static const struct mtk_gate_regs img_cg_regs = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_IMG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate img_clks[] = {
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GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
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GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
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GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
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GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
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};
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static const struct mtk_clk_desc img_desc = {
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.clks = img_clks,
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.num_clks = ARRAY_SIZE(img_clks),
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};
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static const struct of_device_id of_match_clk_mt6797_img[] = {
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{
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.compatible = "mediatek,mt6797-imgsys",
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.data = &img_desc,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_img);
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static struct platform_driver clk_mt6797_img_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6797-img",
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.of_match_table = of_match_clk_mt6797_img,
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},
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};
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module_platform_driver(clk_mt6797_img_drv);
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MODULE_LICENSE("GPL");
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