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20498d52c9
Commit e4c23e19aa
("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpose of propagating a
struct device pointer to the clk API when registering the mtk-gate
clocks to take advantage of Runtime PM when/where needed and where
a power domain is defined in devicetree.
Function mtk_clk_register_gates() then becomes a wrapper around the
new mtk_clk_register_gates_with_dev() function that will simply pass
NULL as struct device: this is essential when registering drivers
with CLK_OF_DECLARE instead of as a platform device, as there will
be no struct device to pass... but we can as well simply have only
one function that always takes such pointer as a param and pass NULL
when unavoidable.
This commit removes the mtk_clk_register_gates() wrapper and renames
mtk_clk_register_gates_with_dev() to the former and all of the calls
to either of the two functions were fixed in all drivers in order to
reflect this change; also, to improve consistency with other kernel
functions, the pointer to struct device was moved as the first param.
Since a lot of MediaTek clock drivers are actually registering as a
platform device, but were still registering the mtk-gate clocks
without passing any struct device to the clock framework, they've
been changed to pass a valid one now, as to make all those platforms
able to use runtime power management where available.
While at it, some much needed indentation changes were also done.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
286 lines
5.8 KiB
C
286 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/printk.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "clk-gate.h"
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struct mtk_clk_gate {
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struct clk_hw hw;
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struct regmap *regmap;
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int set_ofs;
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int clr_ofs;
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int sta_ofs;
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u8 bit;
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};
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static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_gate, hw);
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}
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static u32 mtk_get_clockgating(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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u32 val;
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regmap_read(cg->regmap, cg->sta_ofs, &val);
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return val & BIT(cg->bit);
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}
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static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
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{
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return mtk_get_clockgating(hw) == 0;
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}
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static int mtk_cg_bit_is_set(struct clk_hw *hw)
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{
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return mtk_get_clockgating(hw) != 0;
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}
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static void mtk_cg_set_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
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}
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static void mtk_cg_clr_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
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}
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static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
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}
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static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
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regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
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}
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static int mtk_cg_enable(struct clk_hw *hw)
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{
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mtk_cg_clr_bit(hw);
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return 0;
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}
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static void mtk_cg_disable(struct clk_hw *hw)
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{
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mtk_cg_set_bit(hw);
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}
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static int mtk_cg_enable_inv(struct clk_hw *hw)
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{
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mtk_cg_set_bit(hw);
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return 0;
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}
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static void mtk_cg_disable_inv(struct clk_hw *hw)
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{
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mtk_cg_clr_bit(hw);
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}
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static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
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{
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mtk_cg_clr_bit_no_setclr(hw);
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return 0;
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}
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static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
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{
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mtk_cg_set_bit_no_setclr(hw);
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}
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static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
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{
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mtk_cg_set_bit_no_setclr(hw);
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return 0;
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}
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static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
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{
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mtk_cg_clr_bit_no_setclr(hw);
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}
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const struct clk_ops mtk_clk_gate_ops_setclr = {
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.is_enabled = mtk_cg_bit_is_cleared,
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.enable = mtk_cg_enable,
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.disable = mtk_cg_disable,
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};
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EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
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const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
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.is_enabled = mtk_cg_bit_is_set,
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.enable = mtk_cg_enable_inv,
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.disable = mtk_cg_disable_inv,
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};
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EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
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const struct clk_ops mtk_clk_gate_ops_no_setclr = {
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.is_enabled = mtk_cg_bit_is_cleared,
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.enable = mtk_cg_enable_no_setclr,
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.disable = mtk_cg_disable_no_setclr,
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};
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EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
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const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
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.is_enabled = mtk_cg_bit_is_set,
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.enable = mtk_cg_enable_inv_no_setclr,
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.disable = mtk_cg_disable_inv_no_setclr,
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};
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EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
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static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
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const char *parent_name,
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struct regmap *regmap, int set_ofs,
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int clr_ofs, int sta_ofs, u8 bit,
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const struct clk_ops *ops,
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unsigned long flags)
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{
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struct mtk_clk_gate *cg;
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int ret;
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struct clk_init_data init = {};
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cg = kzalloc(sizeof(*cg), GFP_KERNEL);
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if (!cg)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags | CLK_SET_RATE_PARENT;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.ops = ops;
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cg->regmap = regmap;
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cg->set_ofs = set_ofs;
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cg->clr_ofs = clr_ofs;
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cg->sta_ofs = sta_ofs;
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cg->bit = bit;
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cg->hw.init = &init;
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ret = clk_hw_register(dev, &cg->hw);
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if (ret) {
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kfree(cg);
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return ERR_PTR(ret);
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}
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return &cg->hw;
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}
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static void mtk_clk_unregister_gate(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg;
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if (!hw)
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return;
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cg = to_mtk_clk_gate(hw);
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clk_hw_unregister(hw);
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kfree(cg);
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}
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int mtk_clk_register_gates(struct device *dev, struct device_node *node,
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const struct mtk_gate *clks, int num,
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struct clk_hw_onecell_data *clk_data)
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{
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int i;
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struct clk_hw *hw;
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struct regmap *regmap;
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if (!clk_data)
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return -ENOMEM;
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regmap = device_node_to_regmap(node);
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if (IS_ERR(regmap)) {
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pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
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return PTR_ERR(regmap);
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}
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for (i = 0; i < num; i++) {
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const struct mtk_gate *gate = &clks[i];
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if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
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pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
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node, gate->id);
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continue;
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}
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hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
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regmap,
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gate->regs->set_ofs,
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gate->regs->clr_ofs,
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gate->regs->sta_ofs,
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gate->shift, gate->ops,
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gate->flags);
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if (IS_ERR(hw)) {
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pr_err("Failed to register clk %s: %pe\n", gate->name,
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hw);
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goto err;
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}
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clk_data->hws[gate->id] = hw;
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}
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return 0;
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err:
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while (--i >= 0) {
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const struct mtk_gate *gate = &clks[i];
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if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
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continue;
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mtk_clk_unregister_gate(clk_data->hws[gate->id]);
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clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
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}
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return PTR_ERR(hw);
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}
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EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
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void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
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struct clk_hw_onecell_data *clk_data)
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{
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int i;
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if (!clk_data)
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return;
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for (i = num; i > 0; i--) {
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const struct mtk_gate *gate = &clks[i - 1];
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if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
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continue;
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mtk_clk_unregister_gate(clk_data->hws[gate->id]);
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clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
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}
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}
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EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);
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MODULE_LICENSE("GPL");
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