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96c3c9e78f
This change is required after the e6500 perf support has been added. There are 6 counters in e6500 core instead of 4 in e500 core and the MAX_HWEVENTS counter should be changed accordingly from 4 to 6. Added also runtime check for counters overflow. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/*
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* Performance event support - Freescale embedded specific definitions.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <asm/hw_irq.h>
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#define MAX_HWEVENTS 6
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/* event flags */
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#define FSL_EMB_EVENT_VALID 1
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#define FSL_EMB_EVENT_RESTRICTED 2
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/* upper half of event flags is PMLCb */
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#define FSL_EMB_EVENT_THRESHMUL 0x0000070000000000ULL
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#define FSL_EMB_EVENT_THRESH 0x0000003f00000000ULL
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struct fsl_emb_pmu {
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const char *name;
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int n_counter; /* total number of counters */
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/*
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* The number of contiguous counters starting at zero that
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* can hold restricted events, or zero if there are no
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* restricted events.
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*
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* This isn't a very flexible method of expressing constraints,
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* but it's very simple and is adequate for existing chips.
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*/
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int n_restricted;
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/* Returns event flags and PMLCb (FSL_EMB_EVENT_*) */
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u64 (*xlate_event)(u64 event_id);
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int n_generic;
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int *generic_events;
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int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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};
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int register_fsl_emb_pmu(struct fsl_emb_pmu *);
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