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1c5d2cc719
Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
103 lines
4.0 KiB
Plaintext
103 lines
4.0 KiB
Plaintext
TI PCI Controllers
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PCIe DesignWare Controller
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- compatible: Should be "ti,dra7-pcie" for RC (deprecated)
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Should be "ti,dra7-pcie-ep" for EP (deprecated)
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Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
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Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
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Should be "ti,dra726-pcie-rc" for dra72x in RC mode
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Should be "ti,dra726-pcie-ep" for dra72x in EP mode
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- phys : list of PHY specifiers (used by generic PHY framework)
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- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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where <X> is the instance number of the pcie from the HW spec.
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- num-lanes as specified in ../designware-pcie.txt
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- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
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module and the register offset to specify lane
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selection.
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HOST MODE
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=========
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- reg : Two register ranges as listed in the reg-names property
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- reg-names : The first entry must be "ti-conf" for the TI-specific registers
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The second entry must be "rc-dbics" for the DesignWare PCIe
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registers
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The third entry must be "config" for the PCIe configuration space
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- interrupts : Two interrupt entries must be specified. The first one is for
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main interrupt line and the second for MSI interrupt line.
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- #address-cells,
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#size-cells,
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#interrupt-cells,
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device_type,
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ranges,
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interrupt-map-mask,
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interrupt-map : as specified in ../designware-pcie.txt
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- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
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should contain the register offset within syscon
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and the 2nd argument should contain the bit field
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for setting the bit to enable unaligned
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access.
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DEVICE MODE
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===========
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- reg : Four register ranges as listed in the reg-names property
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- reg-names : "ti-conf" for the TI-specific registers
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"ep_dbics" for the standard configuration registers as
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they are locally accessed within the DIF CS space
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"ep_dbics2" for the standard configuration registers as
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they are locally accessed within the DIF CS2 space
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"addr_space" used to map remote RC address space
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- interrupts : one interrupt entries must be specified for main interrupt.
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- num-ib-windows : number of inbound address translation windows
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- num-ob-windows : number of outbound address translation windows
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- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
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should contain the register offset within syscon
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and the 2nd argument should contain the bit field
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for setting the bit to enable unaligned
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access.
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Optional Property:
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- gpios : Should be added if a GPIO line is required to drive PERST# line
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NOTE: Two DT nodes may be added for each PCI controller; one for host
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mode and another for device mode. So in order for PCI to
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work in host mode, EP mode DT node should be disabled and in order to PCI to
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work in EP mode, host mode DT node should be disabled. Host mode and EP
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mode are mutually exclusive.
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Example:
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axi {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51000000 0x51000000 0x3000
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0x0 0x20000000 0x10000000>;
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pcie@51000000 {
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compatible = "ti,dra7-pcie";
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 232 0x4>, <0 233 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x20013000 0x13000 0 0xffed000>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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