mirror of
https://github.com/torvalds/linux.git
synced 2024-12-24 20:01:55 +00:00
9bc755d2cf
Add devicetree binding documentation for PCIe in EP mode present in AM654 SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
116 lines
4.4 KiB
Plaintext
116 lines
4.4 KiB
Plaintext
TI Keystone PCIe interface
|
|
|
|
Keystone PCI host Controller is based on the Synopsys DesignWare PCI
|
|
hardware version 3.65. It shares common functions with the PCIe DesignWare
|
|
core driver and inherits common properties defined in
|
|
Documentation/devicetree/bindings/pci/designware-pcie.txt
|
|
|
|
Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
|
|
for the details of DesignWare DT bindings. Additional properties are
|
|
described here as well as properties that are not applicable.
|
|
|
|
Required Properties:-
|
|
|
|
compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
|
|
Should be "ti,am654-pcie-rc" for RC on AM654x SoC
|
|
reg: Three register ranges as listed in the reg-names property
|
|
reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
|
|
TI specific application registers, "config" for the
|
|
configuration space address
|
|
|
|
pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
|
|
interrupt-cells: should be set to 1
|
|
interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
|
|
(required if the compatible is "ti,keystone-pcie")
|
|
msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
|
|
(required if the compatible is "ti,am654-pcie-rc".
|
|
|
|
ti,syscon-pcie-id : phandle to the device control module required to set device
|
|
id and vendor id.
|
|
ti,syscon-pcie-mode : phandle to the device control module required to configure
|
|
PCI in either RC mode or EP mode.
|
|
|
|
Example:
|
|
pcie_msi_intc: msi-interrupt-controller {
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
pcie_intc: Interrupt controller device node for Legacy IRQ chip
|
|
interrupt-cells: should be set to 1
|
|
|
|
Example:
|
|
pcie_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
Optional properties:-
|
|
phys: phandle to generic Keystone SerDes PHY for PCI
|
|
phy-names: name of the generic Keystone SerDes PHY for PCI
|
|
- If boot loader already does PCI link establishment, then phys and
|
|
phy-names shouldn't be present.
|
|
interrupts: platform interrupt for error interrupts.
|
|
|
|
DesignWare DT Properties not applicable for Keystone PCI
|
|
|
|
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
|
|
|
|
AM654 PCIe Endpoint
|
|
===================
|
|
|
|
Required Properties:-
|
|
|
|
compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
|
|
reg: Four register ranges as listed in the reg-names property
|
|
reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
|
|
TI specific application registers, "atu" for the
|
|
Address Translation Unit configuration registers and
|
|
"addr_space" used to map remote RC address space
|
|
num-ib-windows: As specified in
|
|
Documentation/devicetree/bindings/pci/designware-pcie.txt
|
|
num-ob-windows: As specified in
|
|
Documentation/devicetree/bindings/pci/designware-pcie.txt
|
|
num-lanes: As specified in
|
|
Documentation/devicetree/bindings/pci/designware-pcie.txt
|
|
power-domains: As documented by the generic PM domain bindings in
|
|
Documentation/devicetree/bindings/power/power_domain.txt.
|
|
ti,syscon-pcie-mode: phandle to the device control module required to configure
|
|
PCI in either RC mode or EP mode.
|
|
|
|
Optional properties:-
|
|
|
|
phys: list of PHY specifiers (used by generic PHY framework)
|
|
phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
|
|
number of lanes as specified in *num-lanes* property.
|
|
("phys" and "phy-names" DT bindings are specified in
|
|
Documentation/devicetree/bindings/phy/phy-bindings.txt)
|
|
interrupts: platform interrupt for error interrupts.
|
|
|
|
pcie-ep {
|
|
compatible = "ti,am654-pcie-ep";
|
|
reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
|
|
<0x10000000 0x8000000>, <0x5506000 0x1000>;
|
|
reg-names = "app", "dbics", "addr_space", "atu";
|
|
power-domains = <&k3_pds 120>;
|
|
ti,syscon-pcie-mode = <&pcie0_mode>;
|
|
num-lanes = <1>;
|
|
num-ib-windows = <16>;
|
|
num-ob-windows = <16>;
|
|
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
|
};
|