mirror of
https://github.com/torvalds/linux.git
synced 2024-12-25 20:32:22 +00:00
82efe43959
- Fix possible memory leak in reserved-memory failure case - Support for DMA parent bus which are not a parent node - Clang -Wunsequenced fix - Remove some unnecessary prints on memory alloc failures - Various printk msg and comment fixes - Update DT schema tools repository location - Convert simple-framebuffer binding to DT schema - Bindings for isl68137 and ir38064 trivial devices - New documentation on binding do's and don't's for binding writers to ignore -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAlzR2jQQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw1+uD/92gu3NHyncELMu7TRHubuM1P5PCAC//BEH ZOG8lopp1v27cPA3aGiSoQu/Uy+JgCjLZWiF9ZiiCvKYaKEdYPB1r7vKWtQ/G2Mk iHJPAgm7uzq0jWTh3J9h6kZkQos1zx9Qh4R81RUdoCY9cGq613Q309Vtj+zluV4Q UVq7fGUL7kDN5LDQh+gTYkX/XBk7I5F5L50RnVcgTIVGCU2DLnRmaXdyrc71N55P w0S2d9eeUIO1N4p4aVnnL1NiY5TjVoh5T6FMWaRzRXr97/YFQVZRBFHKf5AdmUw6 oBbF2wglfWohs5kz30EpuMiqB87vHHy+VbVcybIbZxHHt5wZ7JFNQhGFV74WSt+I +YvmjtKmJZ78ZHjA8wbCno+/DUMkK8Hi5Ft6k7AICDYC6MmAbkBlSIpp10rb6Jfh c4N8Aj7uWv5MRw6dcXkUalE6FBdFq98diFrxSKOlRHwOgDFhoaDBHykAmQmKWvUl hgTjLIcl8FJbsEIyrG5mqlumo6I6/GImpmKqaZ7nD3pzfTKiWi/oVsF4vz5vulY3 Q2dAHLm+UIysI3owbOstnC6tCM+r870FQ8VOPu8Kz0NKoot4ZkUajPr9uVlu5TEM KZLWZ0j4/YnBg9DoPugjkT4YywOGl9VyqFK090pqzseYJ0Lgz7dAl6/QOWkH7C1C yvX2czRWSg== =zBKC -----END PGP SIGNATURE----- Merge tag 'devicetree-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree updates from Rob Herring: - Fix possible memory leak in reserved-memory failure case - Support for DMA parent bus which are not a parent node - Clang -Wunsequenced fix - Remove some unnecessary prints on memory alloc failures - Various printk msg and comment fixes - Update DT schema tools repository location - Convert simple-framebuffer binding to DT schema - Bindings for isl68137 and ir38064 trivial devices - New documentation on binding do's and don't's for binding writers to ignore * tag 'devicetree-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (22 commits) of: unittest: Remove error printing on OOM of: irq: Remove WARN_ON() for kzalloc() failure dt-bindings: pinctrl: fix bias-pull,up typo dt-bindings: Update schema project location to devicetree.org github group of: fix clang -Wunsequenced for be32_to_cpu() of/device.c: fix the wrong comments dt-bindings: Add isl68137 as a trivial device dt-bindings: Add ir38064 as a trivial device of: del redundant type conversion dt-bindings: mfd: axp20x: Add fallback for axp805 of: Improve of_phandle_iterator_next() error message dt-bindings: connector: Spelling mistake dt-bindings: Add schemas for simple-framebuffer of: address: Add support for the parent DMA bus of: address: Retrieve a parent through a callback in __of_translate_address dt-bindings: bus: Add binding for the Allwinner MBUS controller dt-bindings: interconnect: Add a dma interconnect name of: use correct function prototype for of_overlay_fdt_apply() of: reserved_mem: fix reserve memory leak of: property: Document that of_graph_get_endpoint_by_regs needs of_node_put ...
510 lines
14 KiB
YAML
510 lines
14 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/cpus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM CPUs bindings
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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description: |+
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the Devicetree Specification, available from:
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https://www.devicetree.org/specifications/
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with updates for 32-bit and 64-bit ARM systems provided in this document.
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================================
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Convention used in this document
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================================
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This document follows the conventions described in the Devicetree
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Specification, with the addition:
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- square brackets define bitfields, eg reg[7:0] value of the bitfield in
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the reg property contained in bits 7 down to 0
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=====================================
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cpus and cpu node bindings definition
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=====================================
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The ARM architecture, in accordance with the Devicetree Specification,
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requires the cpus and cpu nodes to be present and contain the properties
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described below.
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properties:
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$nodename:
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const: cpus
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description: Container of cpu nodes
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'#address-cells':
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enum: [1, 2]
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description: |
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Definition depends on ARM architecture version and configuration:
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On uniprocessor ARM architectures previous to v7
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value must be 1, to enable a simple enumeration
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scheme for processors that do not have a HW CPU
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identification register.
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On 32-bit ARM 11 MPcore, ARM v7 or later systems
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value must be 1, that corresponds to CPUID/MPIDR
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registers sizes.
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On ARM v8 64-bit systems value should be set to 2,
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that corresponds to the MPIDR_EL1 register size.
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If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
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in the system, #address-cells can be set to 1, since
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MPIDR_EL1[63:32] bits are not used for CPUs
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identification.
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'#size-cells':
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const: 0
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patternProperties:
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'^cpu@[0-9a-f]+$':
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type: object
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properties:
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device_type:
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const: cpu
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reg:
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maxItems: 1
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description: |
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Usage and definition depend on ARM architecture version and
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configuration:
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On uniprocessor ARM architectures previous to v7
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this property is required and must be set to 0.
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On ARM 11 MPcore based systems this property is
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required and matches the CPUID[11:0] register bits.
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Bits [11:0] in the reg cell must be set to
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bits [11:0] in CPU ID register.
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All other bits in the reg cell must be set to 0.
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On 32-bit ARM v7 or later systems this property is
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required and matches the CPU MPIDR[23:0] register
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bits.
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Bits [23:0] in the reg cell must be set to
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bits [23:0] in MPIDR.
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All other bits in the reg cell must be set to 0.
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On ARM v8 64-bit systems this property is required
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and matches the MPIDR_EL1 register affinity bits.
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* If cpus node's #address-cells property is set to 2
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The first reg cell bits [7:0] must be set to
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bits [39:32] of MPIDR_EL1.
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The second reg cell bits [23:0] must be set to
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bits [23:0] of MPIDR_EL1.
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* If cpus node's #address-cells property is set to 1
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The reg cell bits [23:0] must be set to bits [23:0]
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of MPIDR_EL1.
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All other bits in the reg cells must be set to 0.
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compatible:
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items:
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- enum:
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- arm,arm710t
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- arm,arm720t
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- arm,arm740t
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- arm,arm7ej-s
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- arm,arm7tdmi
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- arm,arm7tdmi-s
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- arm,arm9es
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- arm,arm9ej-s
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- arm,arm920t
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- arm,arm922t
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- arm,arm925
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- arm,arm926e-s
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- arm,arm926ej-s
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- arm,arm940t
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- arm,arm946e-s
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- arm,arm966e-s
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- arm,arm968e-s
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- arm,arm9tdmi
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- arm,arm1020e
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- arm,arm1020t
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- arm,arm1022e
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- arm,arm1026ej-s
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- arm,arm1136j-s
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- arm,arm1136jf-s
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- arm,arm1156t2-s
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- arm,arm1156t2f-s
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- arm,arm1176jzf
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- arm,arm1176jz-s
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- arm,arm1176jzf-s
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- arm,arm11mpcore
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- arm,armv8 # Only for s/w models
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- arm,cortex-a5
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- arm,cortex-a7
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- arm,cortex-a8
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- arm,cortex-a9
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- arm,cortex-a12
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- arm,cortex-a15
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- arm,cortex-a17
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- arm,cortex-a53
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- arm,cortex-a57
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- arm,cortex-a72
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- arm,cortex-a73
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- arm,cortex-m0
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- arm,cortex-m0+
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- arm,cortex-m1
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- arm,cortex-m3
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- arm,cortex-m4
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- arm,cortex-r4
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- arm,cortex-r5
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- arm,cortex-r7
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- brcm,brahma-b15
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- brcm,brahma-b53
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- brcm,vulcan
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- cavium,thunder
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- cavium,thunder2
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- faraday,fa526
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- intel,sa110
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- intel,sa1100
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- marvell,feroceon
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- marvell,mohawk
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- marvell,pj4a
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- marvell,pj4b
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- marvell,sheeva-v5
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- marvell,sheeva-v7
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- nvidia,tegra132-denver
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- nvidia,tegra186-denver
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- nvidia,tegra194-carmel
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- qcom,krait
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- qcom,kryo
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- qcom,kryo385
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- qcom,scorpion
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enable-method:
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/string'
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- oneOf:
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# On ARM v8 64-bit this property is required
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- enum:
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- psci
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- spin-table
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# On ARM 32-bit systems this property is optional
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- enum:
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- actions,s500-smp
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- allwinner,sun6i-a31
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- allwinner,sun8i-a23
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- allwinner,sun9i-a80-smp
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- allwinner,sun8i-a83t-smp
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- amlogic,meson8-smp
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- amlogic,meson8b-smp
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- arm,realview-smp
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- brcm,bcm11351-cpu-method
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- brcm,bcm23550
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- brcm,bcm2836-smp
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- brcm,bcm63138
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- brcm,bcm-nsp-smp
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- brcm,brahma-b15
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- marvell,armada-375-smp
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- marvell,armada-380-smp
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- marvell,armada-390-smp
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- marvell,armada-xp-smp
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- marvell,98dx3236-smp
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- mediatek,mt6589-smp
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- mediatek,mt81xx-tz-smp
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- qcom,gcc-msm8660
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- qcom,kpss-acc-v1
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- qcom,kpss-acc-v2
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- renesas,apmu
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- renesas,r9a06g032-smp
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- rockchip,rk3036-smp
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- rockchip,rk3066-smp
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- socionext,milbeaut-m10v-smp
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- ste,dbx500-smp
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cpu-release-addr:
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$ref: '/schemas/types.yaml#/definitions/uint64'
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description:
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Required for systems that have an "enable-method"
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property value of "spin-table".
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On ARM v8 64-bit systems must be a two cell
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property identifying a 64-bit zero-initialised
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memory location.
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cpu-idle-states:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description: |
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List of phandles to idle state nodes supported
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by this cpu (see ./idle-states.txt).
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capacity-dmips-mhz:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description:
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u32 value representing CPU capacity (see ./cpu-capacity.txt) in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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dynamic-power-coefficient:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description:
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A u32 value that represents the running time dynamic
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power coefficient in units of uW/MHz/V^2. The
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coefficient can either be calculated from power
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measurements or derived by analysis.
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The dynamic power consumption of the CPU is
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proportional to the square of the Voltage (V) and
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the clock frequency (f). The coefficient is used to
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calculate the dynamic power as below -
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Pdyn = dynamic-power-coefficient * V^2 * f
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where voltage is in V, frequency is in MHz.
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qcom,saw:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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Specifies the SAW* node associated with this CPU.
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Required for systems that have an "enable-method" property
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value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
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* arm/msm/qcom,saw2.txt
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qcom,acc:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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Specifies the ACC* node associated with this CPU.
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Required for systems that have an "enable-method" property
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value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
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* arm/msm/qcom,kpss-acc.txt
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rockchip,pmu:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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Specifies the syscon node controlling the cpu core power domains.
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Optional for systems that have an "enable-method"
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property value of "rockchip,rk3066-smp"
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While optional, it is the preferred way to get access to
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the cpu-core power-domains.
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required:
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- device_type
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- reg
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- compatible
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dependencies:
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cpu-release-addr: [enable-method]
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rockchip,pmu: [enable-method]
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required:
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- '#address-cells'
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- '#size-cells'
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examples:
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- |
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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};
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};
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- |
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// Example 2 (Cortex-A8 uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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};
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};
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- |
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// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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reg = <0x0>;
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};
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};
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- |
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// Example 4 (ARM Cortex-A57 64-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <2>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x100>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100000101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x101>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100010000 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x10000>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100010001 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x10001>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100010100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x10100>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
|
|
cpu@100010101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57";
|
|
reg = <0x1 0x10101>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x20000000>;
|
|
};
|
|
};
|
|
...
|