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f6bca4d91b
DIPM is unsupported or broken on sunxi. Trying to enable the power
management policy med_power_with_dipm on an Allwinner A20 SoC based board
leads to immediate I/O errors and the attached SATA disk disappears from
the /dev filesystem. A reset (power cycle) is required to make the SATA
controller or disk work again. The A10 and A20 SoC data sheets and manuals
don't mention DIPM at all [1], so it's fair to assume that it's simply not
supported. But even if it was, it should be considered broken and best be
disabled in the ahci_sunxi driver.
[1] https://github.com/allwinner-zh/documents/tree/master/
Fixes: c5754b5220 ("ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to ahci_platform")
Cc: stable@vger.kernel.org
Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de>
Tested-by: Timo Sigurdsson <public_timo.s@silentcreek.de>
Link: https://lore.kernel.org/r/20210614072539.3307-1-public_timo.s@silentcreek.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
307 lines
7.8 KiB
C
307 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Allwinner sunxi AHCI SATA platform driver
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* Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
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* Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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* Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
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* Daniel Wang <danielwang@allwinnertech.com>
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*/
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#include <linux/ahci_platform.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "ahci.h"
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#define DRV_NAME "ahci-sunxi"
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/* Insmod parameters */
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static bool enable_pmp;
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module_param(enable_pmp, bool, 0);
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MODULE_PARM_DESC(enable_pmp,
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"Enable support for sata port multipliers, only use if you use a pmp!");
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#define AHCI_BISTAFR 0x00a0
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#define AHCI_BISTCR 0x00a4
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#define AHCI_BISTFCTR 0x00a8
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#define AHCI_BISTSR 0x00ac
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#define AHCI_BISTDECR 0x00b0
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#define AHCI_DIAGNR0 0x00b4
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#define AHCI_DIAGNR1 0x00b8
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#define AHCI_OOBR 0x00bc
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#define AHCI_PHYCS0R 0x00c0
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#define AHCI_PHYCS1R 0x00c4
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#define AHCI_PHYCS2R 0x00c8
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#define AHCI_TIMER1MS 0x00e0
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#define AHCI_GPARAM1R 0x00e8
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#define AHCI_GPARAM2R 0x00ec
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#define AHCI_PPARAMR 0x00f0
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#define AHCI_TESTR 0x00f4
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#define AHCI_VERSIONR 0x00f8
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#define AHCI_IDR 0x00fc
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#define AHCI_RWCR 0x00fc
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#define AHCI_P0DMACR 0x0170
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#define AHCI_P0PHYCR 0x0178
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#define AHCI_P0PHYSR 0x017c
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static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val &= ~(clr_val);
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writel(reg_val, reg);
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}
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static void sunxi_setbits(void __iomem *reg, u32 set_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val |= set_val;
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writel(reg_val, reg);
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}
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static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val &= ~(clr_val);
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reg_val |= set_val;
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writel(reg_val, reg);
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}
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static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
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{
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return (readl(reg) >> shift) & mask;
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}
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static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
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{
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u32 reg_val;
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int timeout;
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/* This magic is from the original code */
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writel(0, reg_base + AHCI_RWCR);
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msleep(5);
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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(0x7 << 24),
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(0x5 << 24) | BIT(23) | BIT(18));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
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(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
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sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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(0x7 << 20), (0x3 << 20));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
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(0x1f << 5), (0x19 << 5));
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msleep(5);
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sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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timeout = 250; /* Power up takes aprox 50 us */
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do {
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reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
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if (reg_val == 0x02)
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break;
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if (--timeout == 0) {
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dev_err(dev, "PHY power up failed.\n");
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return -EIO;
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}
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udelay(1);
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} while (1);
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sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
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timeout = 100; /* Calibration takes aprox 10 us */
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do {
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reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
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if (reg_val == 0x00)
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break;
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if (--timeout == 0) {
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dev_err(dev, "PHY calibration failed.\n");
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return -EIO;
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}
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udelay(1);
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} while (1);
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msleep(15);
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writel(0x7, reg_base + AHCI_RWCR);
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return 0;
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}
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static void ahci_sunxi_start_engine(struct ata_port *ap)
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{
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ahci_host_priv *hpriv = ap->host->private_data;
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/* Setup DMA before DMA start
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*
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* NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
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* this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
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* User's Guide document (TMS320C674x/OMAP-L1x Processor
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* Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
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* March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
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* p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
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* as equivalent to the following struct:
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*
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* struct AHCI_P0DMACR_t
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* {
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* unsigned TXTS : 4;
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* unsigned RXTS : 4;
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* unsigned TXABL : 4;
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* unsigned RXABL : 4;
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* unsigned Reserved : 16;
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* };
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*
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* TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
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* This field defines the DMA transaction size in DWORDs for
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* transmit (system bus read, device write) operation. [...]
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*
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* RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
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* This field defines the Port DMA transaction size in DWORDs
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* for receive (system bus write, device read) operation. [...]
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*
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* TXABL: Transmit Burst Limit.
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* This field allows software to limit the VBUSP master read
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* burst size. [...]
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*
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* RXABL: Receive Burst Limit.
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* Allows software to limit the VBUSP master write burst
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* size. [...]
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*
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* Reserved: Reserved.
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*
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*
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* NOTE: According to the above document, the following alternative
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* to the code below could perhaps be a better option
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* (or preparation) for possible further improvements later:
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* sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
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* 0x00000033);
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*/
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sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
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/* Start DMA */
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sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
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}
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static const struct ata_port_info ahci_sunxi_port_info = {
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ | ATA_FLAG_NO_DIPM,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_platform_ops,
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};
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static struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ahci_sunxi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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int rc;
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hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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hpriv->start_engine = ahci_sunxi_start_engine;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
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if (rc)
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goto disable_resources;
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hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
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AHCI_HFLAG_YES_NCQ;
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/*
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* The sunxi sata controller seems to be unable to successfully do a
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* soft reset if no pmp is attached, so disable pmp use unless
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* requested, otherwise directly attached disks do not work.
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*/
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if (!enable_pmp)
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hpriv->flags |= AHCI_HFLAG_NO_PMP;
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info,
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&ahci_platform_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ahci_sunxi_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct ahci_host_priv *hpriv = host->private_data;
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int rc;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
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if (rc)
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goto disable_resources;
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rc = ahci_platform_resume_host(dev);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
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ahci_sunxi_resume);
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static const struct of_device_id ahci_sunxi_of_match[] = {
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{ .compatible = "allwinner,sun4i-a10-ahci", },
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{ .compatible = "allwinner,sun8i-r40-ahci", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
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static struct platform_driver ahci_sunxi_driver = {
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.probe = ahci_sunxi_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ahci_sunxi_of_match,
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.pm = &ahci_sunxi_pm_ops,
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},
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};
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module_platform_driver(ahci_sunxi_driver);
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MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
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MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
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MODULE_LICENSE("GPL");
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