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982ac2a7b7
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [Device Tree documentation updated.] Signed-off-by: Robert Richter <rric@kernel.org>
115 lines
2.5 KiB
Plaintext
115 lines
2.5 KiB
Plaintext
/*
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/* First 4KB has pen for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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/ {
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model = "Calxeda ECX-2000";
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compatible = "calxeda,ecx-2000";
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#address-cells = <2>;
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#size-cells = <2>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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};
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memory@0 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
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};
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memory@200000000 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
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};
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soc {
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ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
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timer {
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compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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memory-controller@fff00000 {
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compatible = "calxeda,ecx-2000-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <1>;
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interrupt-controller;
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interrupts = <1 9 0xf04>;
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reg = <0xfff11000 0x1000>,
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<0xfff12000 0x1000>,
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<0xfff14000 0x2000>,
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<0xfff16000 0x2000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
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};
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};
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};
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/include/ "ecx-common.dtsi"
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