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e31cf2f4ca
Patch series "mm: consolidate definitions of page table accessors", v2.
The low level page table accessors (pXY_index(), pXY_offset()) are
duplicated across all architectures and sometimes more than once. For
instance, we have 31 definition of pgd_offset() for 25 supported
architectures.
Most of these definitions are actually identical and typically it boils
down to, e.g.
static inline unsigned long pmd_index(unsigned long address)
{
return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
}
static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
{
return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address);
}
These definitions can be shared among 90% of the arches provided
XYZ_SHIFT, PTRS_PER_XYZ and xyz_page_vaddr() are defined.
For architectures that really need a custom version there is always
possibility to override the generic version with the usual ifdefs magic.
These patches introduce include/linux/pgtable.h that replaces
include/asm-generic/pgtable.h and add the definitions of the page table
accessors to the new header.
This patch (of 12):
The linux/mm.h header includes <asm/pgtable.h> to allow inlining of the
functions involving page table manipulations, e.g. pte_alloc() and
pmd_alloc(). So, there is no point to explicitly include <asm/pgtable.h>
in the files that include <linux/mm.h>.
The include statements in such cases are remove with a simple loop:
for f in $(git grep -l "include <linux/mm.h>") ; do
sed -i -e '/include <asm\/pgtable.h>/ d' $f
done
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Cain <bcain@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Greentime Hu <green.hu@gmail.com>
Cc: Greg Ungerer <gerg@linux-m68k.org>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Guo Ren <guoren@kernel.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Helge Deller <deller@gmx.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Nick Hu <nickhu@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Rich Felker <dalias@libc.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vincent Chen <deanbo422@gmail.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: http://lkml.kernel.org/r/20200514170327.31389-1-rppt@kernel.org
Link: http://lkml.kernel.org/r/20200514170327.31389-2-rppt@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
272 lines
6.4 KiB
C
272 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/kernel/sys_rawhide.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the RAWHIDE.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/core_mcpcia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/*
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* HACK ALERT! only the boot cpu is used for interrupts.
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*/
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/* Note mask bit is true for ENABLED irqs. */
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static unsigned int hose_irq_masks[4] = {
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0xff0000, 0xfe0000, 0xff0000, 0xff0000
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};
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static unsigned int cached_irq_masks[4];
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DEFINE_SPINLOCK(rawhide_irq_lock);
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static inline void
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rawhide_update_irq_hw(int hose, int mask)
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{
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*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
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mb();
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*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
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}
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#define hose_exists(h) \
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(((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
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static inline void
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rawhide_enable_irq(struct irq_data *d)
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{
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unsigned int mask, hose;
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unsigned int irq = d->irq;
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irq -= 16;
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hose = irq / 24;
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if (!hose_exists(hose)) /* if hose non-existent, exit */
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return;
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irq -= hose * 24;
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mask = 1 << irq;
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spin_lock(&rawhide_irq_lock);
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mask |= cached_irq_masks[hose];
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cached_irq_masks[hose] = mask;
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rawhide_update_irq_hw(hose, mask);
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spin_unlock(&rawhide_irq_lock);
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}
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static void
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rawhide_disable_irq(struct irq_data *d)
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{
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unsigned int mask, hose;
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unsigned int irq = d->irq;
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irq -= 16;
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hose = irq / 24;
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if (!hose_exists(hose)) /* if hose non-existent, exit */
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return;
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irq -= hose * 24;
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mask = ~(1 << irq) | hose_irq_masks[hose];
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spin_lock(&rawhide_irq_lock);
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mask &= cached_irq_masks[hose];
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cached_irq_masks[hose] = mask;
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rawhide_update_irq_hw(hose, mask);
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spin_unlock(&rawhide_irq_lock);
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}
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static void
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rawhide_mask_and_ack_irq(struct irq_data *d)
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{
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unsigned int mask, mask1, hose;
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unsigned int irq = d->irq;
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irq -= 16;
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hose = irq / 24;
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if (!hose_exists(hose)) /* if hose non-existent, exit */
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return;
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irq -= hose * 24;
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mask1 = 1 << irq;
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mask = ~mask1 | hose_irq_masks[hose];
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spin_lock(&rawhide_irq_lock);
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mask &= cached_irq_masks[hose];
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cached_irq_masks[hose] = mask;
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rawhide_update_irq_hw(hose, mask);
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/* Clear the interrupt. */
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*(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;
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spin_unlock(&rawhide_irq_lock);
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}
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static struct irq_chip rawhide_irq_type = {
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.name = "RAWHIDE",
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.irq_unmask = rawhide_enable_irq,
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.irq_mask = rawhide_disable_irq,
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.irq_mask_ack = rawhide_mask_and_ack_irq,
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};
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static void
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rawhide_srm_device_interrupt(unsigned long vector)
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* The RAWHIDE SRM console reports PCI interrupts with a vector
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* 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0)
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* shows up as IRQ 24, etc, etc. We adjust it down by 8 to have
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* it line up with the actual bit numbers from the REQ registers,
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* which is how we manage the interrupts/mask. Sigh...
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*
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* Also, PCI #1 interrupts are offset some more... :-(
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*/
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if (irq == 52) {
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/* SCSI on PCI1 is special. */
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irq = 72;
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}
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/* Adjust by which hose it is from. */
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irq -= ((irq + 16) >> 2) & 0x38;
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handle_irq(irq);
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}
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static void __init
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rawhide_init_irq(void)
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{
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struct pci_controller *hose;
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long i;
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mcpcia_init_hoses();
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/* Clear them all; only hoses that exist will be non-zero. */
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for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0;
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for (hose = hose_head; hose; hose = hose->next) {
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unsigned int h = hose->index;
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unsigned int mask = hose_irq_masks[h];
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cached_irq_masks[h] = mask;
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*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;
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*(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;
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}
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for (i = 16; i < 128; ++i) {
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irq_set_chip_and_handler(i, &rawhide_irq_type,
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handle_level_irq);
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irq_set_status_flags(i, IRQ_LEVEL);
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary @ MCPCIA_PCI0_INT_REQ:
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* Bit Meaning
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* 0 Interrupt Line A from slot 2 PCI0
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* 1 Interrupt Line B from slot 2 PCI0
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* 2 Interrupt Line C from slot 2 PCI0
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* 3 Interrupt Line D from slot 2 PCI0
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* 4 Interrupt Line A from slot 3 PCI0
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* 5 Interrupt Line B from slot 3 PCI0
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* 6 Interrupt Line C from slot 3 PCI0
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* 7 Interrupt Line D from slot 3 PCI0
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* 8 Interrupt Line A from slot 4 PCI0
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* 9 Interrupt Line B from slot 4 PCI0
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* 10 Interrupt Line C from slot 4 PCI0
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* 11 Interrupt Line D from slot 4 PCI0
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* 12 Interrupt Line A from slot 5 PCI0
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* 13 Interrupt Line B from slot 5 PCI0
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* 14 Interrupt Line C from slot 5 PCI0
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* 15 Interrupt Line D from slot 5 PCI0
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* 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
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* 17-23 NA
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*
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* IdSel
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* 1 EISA bridge (PCI bus 0 only)
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* 2 PCI option slot 2
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* 3 PCI option slot 3
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* 4 PCI option slot 4
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* 5 PCI option slot 5
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*
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*/
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static int
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rawhide_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[5][5] = {
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/*INT INTA INTB INTC INTD */
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{ 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */
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{ 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */
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{ 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */
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{ 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */
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{ 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */
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};
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const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5;
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struct pci_controller *hose = dev->sysdata;
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int irq = COMMON_TABLE_LOOKUP;
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if (irq >= 0)
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irq += 24 * hose->index;
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return irq;
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}
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/*
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* The System Vector
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*/
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struct alpha_machine_vector rawhide_mv __initmv = {
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.vector_name = "Rawhide",
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DO_EV5_MMU,
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DO_DEFAULT_RTC,
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DO_MCPCIA_IO,
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.machine_check = mcpcia_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = MCPCIA_DEFAULT_MEM_BASE,
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.pci_dac_offset = MCPCIA_DAC_OFFSET,
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.nr_irqs = 128,
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.device_interrupt = rawhide_srm_device_interrupt,
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.init_arch = mcpcia_init_arch,
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.init_irq = rawhide_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = common_init_pci,
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.kill_arch = NULL,
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.pci_map_irq = rawhide_map_irq,
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.pci_swizzle = common_swizzle,
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};
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ALIAS_MV(rawhide)
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