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b5ddb6d547
PAE40 confiuration in hardware extends some of the address registers for TLB/cache ops to 2 words. So far kernel was NOT setting the higher word if feature was not enabled in software which is wrong. Those need to be set to 0 in such case. Normally this would be done in the cache flush / tlb ops, however since these registers only exist conditionally, this would have to be conditional to a flag being set on boot which is expensive/ugly - specially for the more common case of PAE exists but not in use. Optimize that by zero'ing them once at boot - nobody will write to them afterwards Cc: stable@vger.kernel.org #4.4+ Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_MMU_H
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#define _ASM_ARC_MMU_H
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#ifndef __ASSEMBLY__
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#include <linux/threads.h> /* NR_CPUS */
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#endif
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#elif defined(CONFIG_ARC_MMU_V4)
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#define CONFIG_ARC_MMU_VER 4
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#endif
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/* MMU Management regs */
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#define ARC_REG_MMU_BCR 0x06f
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#if (CONFIG_ARC_MMU_VER < 4)
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
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#define ARC_REG_TLBINDEX 0x407
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#define ARC_REG_TLBCOMMAND 0x408
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#define ARC_REG_PID 0x409
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#define ARC_REG_SCRATCH_DATA0 0x418
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#else
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#define ARC_REG_TLBPD0 0x460
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#define ARC_REG_TLBPD1 0x461
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#define ARC_REG_TLBPD1HI 0x463
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#define ARC_REG_TLBINDEX 0x464
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#define ARC_REG_TLBCOMMAND 0x465
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#define ARC_REG_PID 0x468
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#define ARC_REG_SCRATCH_DATA0 0x46c
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#endif
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/* Bits in MMU PID register */
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#define __TLB_ENABLE (1 << 31)
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#define __PROG_ENABLE (1 << 30)
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#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
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/* Error code if probe fails */
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#define TLB_LKUP_ERR 0x80000000
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#if (CONFIG_ARC_MMU_VER < 4)
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
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#else
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
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#endif
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/* TLB Commands */
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#define TLBWrite 0x1
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#define TLBRead 0x2
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#define TLBGetIndex 0x3
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#define TLBProbe 0x4
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#if (CONFIG_ARC_MMU_VER >= 2)
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#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
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#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
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#endif
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#if (CONFIG_ARC_MMU_VER >= 4)
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#define TLBInsertEntry 0x7
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#define TLBDeleteEntry 0x8
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#endif
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
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} mm_context_t;
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#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
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void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
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#else
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#define tlb_paranoid_check(a, b)
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#endif
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void arc_mmu_init(void);
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extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
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void read_decode_mmu_bcr(void);
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static inline int is_pae40_enabled(void)
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{
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return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
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}
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extern int pae40_exist_but_not_enab(void);
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#endif /* !__ASSEMBLY__ */
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#endif
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