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5a6704454a
BCM6338 and BCM6348 have a message control register width of 8 bits, instead of 16-bits like what the SPI driver assumes right now. Also the SPI message type shift value of 14 is actually 6 for these SoCs. This resulted in transmit FIFO corruption because we were writing 16-bits to an 8-bits wide register, thus spanning on the first byte of the transmit FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo(). Fix this by passing the message control register width and message type shift through platform data back to the SPI driver so that it can use it properly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Cc: jonas.gorski@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/3983/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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| .. | ||
| boards | ||
| clk.c | ||
| cpu.c | ||
| cs.c | ||
| dev-dsp.c | ||
| dev-enet.c | ||
| dev-flash.c | ||
| dev-pcmcia.c | ||
| dev-rng.c | ||
| dev-spi.c | ||
| dev-uart.c | ||
| dev-wdt.c | ||
| early_printk.c | ||
| gpio.c | ||
| irq.c | ||
| Kconfig | ||
| Makefile | ||
| Platform | ||
| prom.c | ||
| setup.c | ||
| timer.c | ||