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For configurations that have aliasing in the data cache but not in the instruction cache, we don't need to flush the instruction cache. Thus, we didn't define the macros to flush the instruction cache. Some cache-flush functions, howerver, were using those macros. Signed-off-by: Chris Zankel <chris@zankel.net>
156 lines
4.6 KiB
C
156 lines
4.6 KiB
C
/*
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* include/asm-xtensa/cacheflush.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHEFLUSH_H
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#define _XTENSA_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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/*
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* Lo-level routines for cache flushing.
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*
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* invalidate data or instruction cache:
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*
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* __invalidate_icache_all()
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* __invalidate_icache_page(adr)
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* __invalidate_dcache_page(adr)
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* __invalidate_icache_range(from,size)
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* __invalidate_dcache_range(from,size)
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*
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* flush data cache:
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*
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* __flush_dcache_page(adr)
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*
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* flush and invalidate data cache:
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*
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* __flush_invalidate_dcache_all()
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* __flush_invalidate_dcache_page(adr)
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* __flush_invalidate_dcache_range(from,size)
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*
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* specials for cache aliasing:
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*
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* __flush_invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_icache_page_alias(vaddr,paddr)
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*/
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extern void __invalidate_dcache_all(void);
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extern void __invalidate_icache_all(void);
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extern void __invalidate_dcache_page(unsigned long);
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extern void __invalidate_icache_page(unsigned long);
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extern void __invalidate_icache_range(unsigned long, unsigned long);
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extern void __invalidate_dcache_range(unsigned long, unsigned long);
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#if XCHAL_DCACHE_IS_WRITEBACK
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extern void __flush_invalidate_dcache_all(void);
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extern void __flush_dcache_page(unsigned long);
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extern void __flush_dcache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#else
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# define __flush_dcache_range(p,s) do { } while(0)
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# define __flush_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
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# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
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#endif
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
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#endif
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#if (ICACHE_WAY_SIZE > PAGE_SIZE)
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extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
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#else
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# define __invalidate_icache_page_alias(v,p) do { } while(0)
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#endif
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/*
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* We have physically tagged caches - nothing to do here -
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* unless we have cache aliasing.
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*
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* Pages can get remapped. Because this might change the 'color' of that page,
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* we have to flush the cache before the PTE is changed.
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* (see also Documentation/cachetlb.txt)
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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#define flush_cache_all() \
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do { \
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__flush_invalidate_dcache_all(); \
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__invalidate_icache_all(); \
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} while (0)
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#define flush_cache_mm(mm) flush_cache_all()
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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#define flush_cache_vmap(start,end) flush_cache_all()
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#define flush_cache_vunmap(start,end) flush_cache_all()
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extern void flush_dcache_page(struct page*);
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extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
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#else
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_vmap(start,end) do { } while (0)
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#define flush_cache_vunmap(start,end) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_cache_page(vma,addr,pfn) do { } while (0)
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#define flush_cache_range(vma,start,end) do { } while (0)
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#endif
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/* Ensure consistency between data and instruction cache. */
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#define flush_icache_range(start,end) \
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do { \
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__flush_dcache_range(start, (end) - (start)); \
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__invalidate_icache_range(start,(end) - (start)); \
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} while (0)
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/* This is not required, see Documentation/cachetlb.txt */
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#define flush_icache_page(vma,page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void copy_to_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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extern void copy_from_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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#else
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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__flush_dcache_range((unsigned long) dst, len); \
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__invalidate_icache_range((unsigned long) dst, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_CACHEFLUSH_H */
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