Brad Volkin c9224faa59 drm/i915: Add some L3 registers to the parser whitelist ... Beignet needs these in order to program the L3 cache config for OpenCL workloads, particularly when using SLM. Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-06-18 00:48:35 +02:00
..
drm	drm/i915: Add some L3 registers to the parser whitelist	2014-06-18 00:48:35 +02:00
host1x	gpu: host1x: Rename internal functions for clarity	2014-06-05 23:10:30 +02:00
ipu-v3	gpu: ipu-v3: Register the CSI modules	2014-06-04 11:07:12 +02:00
vga	vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled	2014-06-02 10:25:08 -04:00
Makefile	gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging	2014-06-04 11:06:52 +02:00