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c917a36f5f
vaddr used to index the cache was clipped from the wrong end, and thus would potentially fail to flush the correct lines. The problem was dorment for so long because up until the recent optimizations it was only used for ptrace break-point only flushes. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
614 lines
18 KiB
C
614 lines
18 KiB
C
/*
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* ARC700 VIPT Cache Management
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
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* -flush_cache_dup_mm (fork)
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* -likewise for flush_cache_mm (exit/execve)
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* -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
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*
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* vineetg: Apr 2011
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* -Now that MMU can support larger pg sz (16K), the determiniation of
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* aliasing shd not be based on assumption of 8k pg
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*
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* vineetg: Mar 2011
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* -optimised version of flush_icache_range( ) for making I/D coherent
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* when vaddr is available (agnostic of num of aliases)
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*
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* vineetg: Mar 2011
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* -Added documentation about I-cache aliasing on ARC700 and the way it
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* was handled up until MMU V2.
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* -Spotted a three year old bug when killing the 4 aliases, which needs
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* bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
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* instead of paddr | {0x00, 0x01, 0x10, 0x11}
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* (Rajesh you owe me one now)
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*
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* vineetg: Dec 2010
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* -Off-by-one error when computing num_of_lines to flush
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* This broke signal handling with bionic which uses synthetic sigret stub
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*
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* vineetg: Mar 2010
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* -GCC can't generate ZOL for core cache flush loops.
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* Conv them into iterations based as opposed to while (start < end) types
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*
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* Vineetg: July 2009
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* -In I-cache flush routine we used to chk for aliasing for every line INV.
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* Instead now we setup routines per cache geometry and invoke them
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* via function pointers.
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*
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* Vineetg: Jan 2009
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* -Cache Line flush routines used to flush an extra line beyond end addr
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* because check was while (end >= start) instead of (end > start)
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* =Some call sites had to work around by doing -1, -4 etc to end param
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* =Some callers didnt care. This was spec bad in case of INV routines
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* which would discard valid data (cause of the horrible ext2 bug
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* in ARC IDE driver)
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*
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* vineetg: June 11th 2008: Fixed flush_icache_range( )
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* -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
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* to be flushed, which it was not doing.
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* -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
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* however ARC cache maintenance OPs require PHY addr. Thus need to do
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* vmalloc_to_phy.
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* -Also added optimisation there, that for range > PAGE SIZE we flush the
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* entire cache in one shot rather than line by line. For e.g. a module
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* with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
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* while cache is only 16 or 32k.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/cache.h>
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#include <linux/mmu_context.h>
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#include <linux/syscalls.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/cachectl.h>
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#include <asm/setup.h>
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char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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unsigned int c = smp_processor_id();
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#define PR_CACHE(p, enb, str) \
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{ \
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if (!(p)->ver) \
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n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
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else \
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n += scnprintf(buf + n, len - n, \
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str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
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TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
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enb ? "" : "DISABLED (kernel-build)"); \
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}
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PR_CACHE(&cpuinfo_arc700[c].icache, __CONFIG_ARC_HAS_ICACHE, "I-Cache");
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PR_CACHE(&cpuinfo_arc700[c].dcache, __CONFIG_ARC_HAS_DCACHE, "D-Cache");
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return buf;
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}
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/*
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* Read the Cache Build Confuration Registers, Decode them and save into
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* the cpuinfo structure for later use.
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* No Validation done here, simply read/convert the BCRs
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*/
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void __cpuinit read_decode_cache_bcr(void)
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{
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struct bcr_cache ibcr, dbcr;
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struct cpuinfo_arc_cache *p_ic, *p_dc;
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unsigned int cpu = smp_processor_id();
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p_ic = &cpuinfo_arc700[cpu].icache;
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READ_BCR(ARC_REG_IC_BCR, ibcr);
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if (ibcr.config == 0x3)
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p_ic->assoc = 2;
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p_ic->line_len = 8 << ibcr.line_len;
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p_ic->sz = 0x200 << ibcr.sz;
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p_ic->ver = ibcr.ver;
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p_dc = &cpuinfo_arc700[cpu].dcache;
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READ_BCR(ARC_REG_DC_BCR, dbcr);
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if (dbcr.config == 0x2)
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p_dc->assoc = 4;
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p_dc->line_len = 16 << dbcr.line_len;
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p_dc->sz = 0x200 << dbcr.sz;
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p_dc->ver = dbcr.ver;
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}
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/*
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* 1. Validate the Cache Geomtery (compile time config matches hardware)
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* 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
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* (aliasing D-cache configurations are not supported YET)
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* 3. Enable the Caches, setup default flush mode for D-Cache
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* 3. Calculate the SHMLBA used by user space
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*/
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void __cpuinit arc_cache_init(void)
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{
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unsigned int temp;
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
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struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
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int way_pg_ratio = way_pg_ratio;
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char str[256];
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printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
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if (!ic->ver)
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goto chk_dc;
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#ifdef CONFIG_ARC_HAS_ICACHE
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/* 1. Confirm some of I-cache params which Linux assumes */
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if ((ic->assoc != ARC_ICACHE_WAYS) ||
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(ic->line_len != ARC_ICACHE_LINE_LEN)) {
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panic("Cache H/W doesn't match kernel Config");
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}
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#if (CONFIG_ARC_MMU_VER > 2)
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if (ic->ver != 3) {
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if (running_on_hw)
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panic("Cache ver doesn't match MMU ver\n");
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/* For ISS - suggest the toggles to use */
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pr_err("Use -prop=icache_version=3,-prop=dcache_version=3\n");
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}
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#endif
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#endif
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/* Enable/disable I-Cache */
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temp = read_aux_reg(ARC_REG_IC_CTRL);
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#ifdef CONFIG_ARC_HAS_ICACHE
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temp &= ~IC_CTRL_CACHE_DISABLE;
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#else
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temp |= IC_CTRL_CACHE_DISABLE;
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#endif
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write_aux_reg(ARC_REG_IC_CTRL, temp);
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chk_dc:
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if (!dc->ver)
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return;
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#ifdef CONFIG_ARC_HAS_DCACHE
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if ((dc->assoc != ARC_DCACHE_WAYS) ||
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(dc->line_len != ARC_DCACHE_LINE_LEN)) {
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panic("Cache H/W doesn't match kernel Config");
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}
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/* check for D-Cache aliasing */
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if ((dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE)
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panic("D$ aliasing not handled right now\n");
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#endif
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/* Set the default Invalidate Mode to "simpy discard dirty lines"
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* as this is more frequent then flush before invalidate
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* Ofcourse we toggle this default behviour when desired
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*/
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temp = read_aux_reg(ARC_REG_DC_CTRL);
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temp &= ~DC_CTRL_INV_MODE_FLUSH;
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#ifdef CONFIG_ARC_HAS_DCACHE
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/* Enable D-Cache: Clear Bit 0 */
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write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
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#else
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/* Flush D cache */
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write_aux_reg(ARC_REG_DC_FLSH, 0x1);
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/* Disable D cache */
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write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
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#endif
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return;
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}
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#define OP_INV 0x1
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#define OP_FLUSH 0x2
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#define OP_FLUSH_N_INV 0x3
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#ifdef CONFIG_ARC_HAS_DCACHE
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/***************************************************************
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* Machine specific helpers for Entire D-Cache or Per Line ops
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*/
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static inline void wait_for_flush(void)
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{
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while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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}
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/*
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* Operation on Entire D-Cache
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* @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
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* Note that constant propagation ensures all the checks are gone
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* in generated code
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*/
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static inline void __dc_entire_op(const int cacheop)
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{
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unsigned long flags, tmp = tmp;
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int aux;
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local_irq_save(flags);
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if (cacheop == OP_FLUSH_N_INV) {
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/* Dcache provides 2 cmd: FLUSH or INV
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* INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
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* flush-n-inv is achieved by INV cmd but with IM=1
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* Default INV sub-mode is DISCARD, which needs to be toggled
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*/
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tmp = read_aux_reg(ARC_REG_DC_CTRL);
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write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
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}
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_REG_DC_IVDC;
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else
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aux = ARC_REG_DC_FLSH;
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write_aux_reg(aux, 0x1);
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if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
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wait_for_flush();
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/* Switch back the DISCARD ONLY Invalidate mode */
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if (cacheop == OP_FLUSH_N_INV)
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write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
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local_irq_restore(flags);
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}
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/*
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* Per Line Operation on D-Cache
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* Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete
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* It's sole purpose is to help gcc generate ZOL
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*/
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static inline void __dc_line_loop(unsigned long start, unsigned long sz,
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int aux_reg)
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{
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int num_lines, slack;
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/* Ensure we properly floor/ceil the non-line aligned/sized requests
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* and have @start - aligned to cache line and integral @num_lines.
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* This however can be avoided for page sized since:
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* -@start will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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slack = start & ~DCACHE_LINE_MASK;
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sz += slack;
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start -= slack;
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}
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num_lines = DIV_ROUND_UP(sz, ARC_DCACHE_LINE_LEN);
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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/*
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* Just as for I$, in MMU v3, D$ ops also require
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* "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops
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* But we pass phy addr for both. This works since Linux
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* doesn't support aliasing configs for D$, yet.
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* Thus paddr is enough to provide both tag and index.
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*/
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write_aux_reg(ARC_REG_DC_PTAG, start);
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#endif
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write_aux_reg(aux_reg, start);
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start += ARC_DCACHE_LINE_LEN;
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}
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}
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/*
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* D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
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*/
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static inline void __dc_line_op(unsigned long start, unsigned long sz,
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const int cacheop)
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{
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unsigned long flags, tmp = tmp;
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int aux;
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local_irq_save(flags);
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if (cacheop == OP_FLUSH_N_INV) {
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/*
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* Dcache provides 2 cmd: FLUSH or INV
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* INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
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* flush-n-inv is achieved by INV cmd but with IM=1
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* Default INV sub-mode is DISCARD, which needs to be toggled
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*/
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tmp = read_aux_reg(ARC_REG_DC_CTRL);
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write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
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}
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if (cacheop & OP_INV) /* Inv / flush-n-inv use same cmd reg */
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aux = ARC_REG_DC_IVDL;
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else
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aux = ARC_REG_DC_FLDL;
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__dc_line_loop(start, sz, aux);
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if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
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wait_for_flush();
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/* Switch back the DISCARD ONLY Invalidate mode */
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if (cacheop == OP_FLUSH_N_INV)
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write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
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local_irq_restore(flags);
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}
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#else
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#define __dc_entire_op(cacheop)
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#define __dc_line_op(start, sz, cacheop)
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#endif /* CONFIG_ARC_HAS_DCACHE */
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#ifdef CONFIG_ARC_HAS_ICACHE
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/*
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* I-Cache Aliasing in ARC700 VIPT caches
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*
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* ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
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* The orig Cache Management Module "CDU" only required paddr to invalidate a
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* certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
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* Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
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* the exact same line.
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*
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* However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
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* paddr alone could not be used to correctly index the cache.
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*
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* ------------------
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* MMU v1/v2 (Fixed Page Size 8k)
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* ------------------
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* The solution was to provide CDU with these additonal vaddr bits. These
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* would be bits [x:13], x would depend on cache-geometry, 13 comes from
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* standard page size of 8k.
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* H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
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* of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
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* orig 5 bits of paddr were anyways ignored by CDU line ops, as they
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* represent the offset within cache-line. The adv of using this "clumsy"
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* interface for additional info was no new reg was needed in CDU programming
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* model.
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*
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* 17:13 represented the max num of bits passable, actual bits needed were
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* fewer, based on the num-of-aliases possible.
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* -for 2 alias possibility, only bit 13 needed (32K cache)
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* -for 4 alias possibility, bits 14:13 needed (64K cache)
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*
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* ------------------
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* MMU v3
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* ------------------
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* This ver of MMU supports variable page sizes (1k-16k): although Linux will
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* only support 8k (default), 16k and 4k.
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* However from hardware perspective, smaller page sizes aggrevate aliasing
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* meaning more vaddr bits needed to disambiguate the cache-line-op ;
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* the existing scheme of piggybacking won't work for certain configurations.
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* Two new registers IC_PTAG and DC_PTAG inttoduced.
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* "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
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*/
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/***********************************************************
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* Machine specific helper for per line I-Cache invalidate.
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*/
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static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
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unsigned long sz)
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{
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unsigned long flags;
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int num_lines, slack;
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unsigned int addr;
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/*
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* Ensure we properly floor/ceil the non-line aligned/sized requests:
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* However page sized flushes can be compile time optimised.
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* -@phy_start will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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slack = phy_start & ~ICACHE_LINE_MASK;
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sz += slack;
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phy_start -= slack;
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}
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num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
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#if (CONFIG_ARC_MMU_VER > 2)
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vaddr &= ICACHE_LINE_MASK;
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addr = phy_start;
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#else
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/* bits 17:13 of vaddr go as bits 4:0 of paddr */
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addr = phy_start | ((vaddr >> 13) & 0x1F);
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#endif
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local_irq_save(flags);
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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/* tag comes from phy addr */
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write_aux_reg(ARC_REG_IC_PTAG, addr);
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/* index bits come from vaddr */
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write_aux_reg(ARC_REG_IC_IVIL, vaddr);
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vaddr += ARC_ICACHE_LINE_LEN;
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#else
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/* paddr contains stuffed vaddrs bits */
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write_aux_reg(ARC_REG_IC_IVIL, addr);
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#endif
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addr += ARC_ICACHE_LINE_LEN;
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}
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local_irq_restore(flags);
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}
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#else
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#define __ic_line_inv_vaddr(pstart, vstart, sz)
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#endif /* CONFIG_ARC_HAS_ICACHE */
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/***********************************************************
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* Exported APIs
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*/
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void flush_dcache_page(struct page *page)
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{
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/* Make a note that dcache is not yet flushed for this page */
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set_bit(PG_arch_1, &page->flags);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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void dma_cache_wback_inv(unsigned long start, unsigned long sz)
|
|
{
|
|
__dc_line_op(start, sz, OP_FLUSH_N_INV);
|
|
}
|
|
EXPORT_SYMBOL(dma_cache_wback_inv);
|
|
|
|
void dma_cache_inv(unsigned long start, unsigned long sz)
|
|
{
|
|
__dc_line_op(start, sz, OP_INV);
|
|
}
|
|
EXPORT_SYMBOL(dma_cache_inv);
|
|
|
|
void dma_cache_wback(unsigned long start, unsigned long sz)
|
|
{
|
|
__dc_line_op(start, sz, OP_FLUSH);
|
|
}
|
|
EXPORT_SYMBOL(dma_cache_wback);
|
|
|
|
/*
|
|
* This is API for making I/D Caches consistent when modifying
|
|
* kernel code (loadable modules, kprobes, kgdb...)
|
|
* This is called on insmod, with kernel virtual address for CODE of
|
|
* the module. ARC cache maintenance ops require PHY address thus we
|
|
* need to convert vmalloc addr to PHY addr
|
|
*/
|
|
void flush_icache_range(unsigned long kstart, unsigned long kend)
|
|
{
|
|
unsigned int tot_sz, off, sz;
|
|
unsigned long phy, pfn;
|
|
|
|
/* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
|
|
|
|
/* This is not the right API for user virtual address */
|
|
if (kstart < TASK_SIZE) {
|
|
BUG_ON("Flush icache range for user virtual addr space");
|
|
return;
|
|
}
|
|
|
|
/* Shortcut for bigger flush ranges.
|
|
* Here we don't care if this was kernel virtual or phy addr
|
|
*/
|
|
tot_sz = kend - kstart;
|
|
if (tot_sz > PAGE_SIZE) {
|
|
flush_cache_all();
|
|
return;
|
|
}
|
|
|
|
/* Case: Kernel Phy addr (0x8000_0000 onwards) */
|
|
if (likely(kstart > PAGE_OFFSET)) {
|
|
/*
|
|
* The 2nd arg despite being paddr will be used to index icache
|
|
* This is OK since no alternate virtual mappings will exist
|
|
* given the callers for this case: kprobe/kgdb in built-in
|
|
* kernel code only.
|
|
*/
|
|
__sync_icache_dcache(kstart, kstart, kend - kstart);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
|
|
* (1) ARC Cache Maintenance ops only take Phy addr, hence special
|
|
* handling of kernel vaddr.
|
|
*
|
|
* (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
|
|
* it still needs to handle a 2 page scenario, where the range
|
|
* straddles across 2 virtual pages and hence need for loop
|
|
*/
|
|
while (tot_sz > 0) {
|
|
off = kstart % PAGE_SIZE;
|
|
pfn = vmalloc_to_pfn((void *)kstart);
|
|
phy = (pfn << PAGE_SHIFT) + off;
|
|
sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
|
|
__sync_icache_dcache(phy, kstart, sz);
|
|
kstart += sz;
|
|
tot_sz -= sz;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* General purpose helper to make I and D cache lines consistent.
|
|
* @paddr is phy addr of region
|
|
* @vaddr is typically user or kernel vaddr (vmalloc)
|
|
* Howver in one instance, flush_icache_range() by kprobe (for a breakpt in
|
|
* builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
|
|
* use a paddr to index the cache (despite VIPT). This is fine since since a
|
|
* built-in kernel page will not have any virtual mappings (not even kernel)
|
|
* kprobe on loadable module is different as it will have kvaddr.
|
|
*/
|
|
void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
__ic_line_inv_vaddr(paddr, vaddr, len);
|
|
__dc_line_op(paddr, len, OP_FLUSH);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/* wrapper to compile time eliminate alignment checks in flush loop */
|
|
void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
|
|
{
|
|
__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
|
|
}
|
|
|
|
void __flush_dcache_page(unsigned long paddr)
|
|
{
|
|
__dc_line_op(paddr, PAGE_SIZE, OP_FLUSH_N_INV);
|
|
}
|
|
|
|
void flush_icache_all(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
write_aux_reg(ARC_REG_IC_IVIC, 1);
|
|
|
|
/* lr will not complete till the icache inv operation is not over */
|
|
read_aux_reg(ARC_REG_IC_CTRL);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
noinline void flush_cache_all(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
flush_icache_all();
|
|
__dc_entire_op(OP_FLUSH_N_INV);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
/**********************************************************************
|
|
* Explicit Cache flush request from user space via syscall
|
|
* Needed for JITs which generate code on the fly
|
|
*/
|
|
SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
|
|
{
|
|
/* TBD: optimize this */
|
|
flush_cache_all();
|
|
return 0;
|
|
}
|