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26955c07dc
Devices which utilise DMA use the same device numbers for transmitting and receiving. In this patch we encode the source and destination information into one single attribute. We can subsequently exploit the direction attribute to see which of the transfer directions are being described. This also lessens the burden on platform data. Cc: Dan Williams <djbw@fb.com> Cc: Per Forlin <per.forlin@stericsson.com> Cc: Rabin Vincent <rabin@rab.in> Acked-by: Vinod Koul <vinod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/*
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* arch/arm/mach-ux500/ste_dma40_db8500.h
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* DB8500-SoC-specific configuration for DMA40
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*
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* Copyright (C) ST-Ericsson 2007-2010
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* License terms: GNU General Public License (GPL) version 2
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* Author: Per Friden <per.friden@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#ifndef STE_DMA40_DB8500_H
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#define STE_DMA40_DB8500_H
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#define DB8500_DMA_NR_DEV 64
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/*
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* Unless otherwise specified, all channels numbers are used for
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* TX & RX, and can be used for either source or destination
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* channels.
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*/
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enum dma_dev_type {
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DB8500_DMA_DEV0_SPI0 = 0,
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DB8500_DMA_DEV1_SD_MMC0 = 1,
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DB8500_DMA_DEV2_SD_MMC1 = 2,
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DB8500_DMA_DEV3_SD_MMC2 = 3,
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DB8500_DMA_DEV4_I2C1 = 4,
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DB8500_DMA_DEV5_I2C3 = 5,
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DB8500_DMA_DEV6_I2C2 = 6,
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DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */
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DB8500_DMA_DEV8_SSP0 = 8,
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DB8500_DMA_DEV9_SSP1 = 9,
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DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
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DB8500_DMA_DEV11_UART2 = 11,
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DB8500_DMA_DEV12_UART1 = 12,
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DB8500_DMA_DEV13_UART0 = 13,
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DB8500_DMA_DEV14_MSP2 = 14,
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DB8500_DMA_DEV15_I2C0 = 15,
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DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
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DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
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DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
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DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
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DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
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DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
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DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
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DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
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DB8500_DMA_DEV24_SXA0 = 24,
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DB8500_DMA_DEV25_SXA1 = 25,
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DB8500_DMA_DEV26_SXA2 = 26,
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DB8500_DMA_DEV27_SXA3 = 27,
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DB8500_DMA_DEV28_SD_MM2 = 28,
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DB8500_DMA_DEV29_SD_MM0 = 29,
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DB8500_DMA_DEV30_MSP1 = 30,
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/* On DB8500v2, MSP3 RX replaces MSP1 RX */
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DB8500_DMA_DEV30_MSP3 = 30,
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DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
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DB8500_DMA_DEV32_SD_MM1 = 32,
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DB8500_DMA_DEV33_SPI2 = 33,
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DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
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DB8500_DMA_DEV35_SPI1 = 35,
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DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
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DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
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DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
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DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
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DB8500_DMA_DEV40_SPI3 = 40,
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DB8500_DMA_DEV41_SD_MM3 = 41,
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DB8500_DMA_DEV42_SD_MM4 = 42,
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DB8500_DMA_DEV43_SD_MM5 = 43,
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DB8500_DMA_DEV44_SXA4 = 44,
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DB8500_DMA_DEV45_SXA5 = 45,
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DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
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DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
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DB8500_DMA_DEV48_CAC1 = 48,
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DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
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DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
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DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
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DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
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DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
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DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
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DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
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/* 56 -> 60 are channels reserved for memcpy only */
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DB8500_DMA_DEV61_CAC0 = 61,
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DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
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DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
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};
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#endif
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