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Add driver for Amazon's Annapurna Labs PCIe host controller. The controller is based on DesignWare's IP. The controller doesn't support accessing the Root Port's config space via ECAM, so we obtain its base address via an AMZN0001 device. Furthermore, the DesignWare PCIe controller doesn't filter out config transactions sent to devices 1 and up on its bus, so they are filtered by the driver. All subordinate buses do support ECAM access. Implementing specific PCI config access functions involves: - Adding an init function to obtain the Root Port's base address from an AMZN0001 device. - Adding a new entry in the MCFG quirk array. [bhelgaas: Note that there is no Kconfig option for this driver because it is only intended for use with the generic ACPI host bridge driver. This driver is only needed because the DesignWare IP doesn't completely support ECAM access to the root bus.] Link: https://lore.kernel.org/lkml/1553774276-24675-1-git-send-email-jonnyc@amazon.com Co-developed-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
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* such as Graviton and Alpine)
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*
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* Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Author: Jonathan Chocron <jonnyc@amazon.com>
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*/
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/pci-acpi.h>
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#include "../../pci.h"
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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struct al_pcie_acpi {
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void __iomem *dbi_base;
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};
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static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct al_pcie_acpi *pcie = cfg->priv;
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void __iomem *dbi_base = pcie->dbi_base;
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if (bus->number == cfg->busr.start) {
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/*
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* The DW PCIe core doesn't filter out transactions to other
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* devices/functions on the root bus num, so we do this here.
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*/
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if (PCI_SLOT(devfn) > 0)
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return NULL;
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else
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return dbi_base + where;
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}
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return pci_ecam_map_bus(bus, devfn, where);
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}
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static int al_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct al_pcie_acpi *al_pcie;
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struct resource *res;
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int ret;
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al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
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if (!al_pcie)
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return -ENOMEM;
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res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);
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if (ret) {
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dev_err(dev, "can't get rc dbi base address for SEG %d\n",
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root->segment);
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return ret;
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}
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dev_dbg(dev, "Root port dbi res: %pR\n", res);
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al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(al_pcie->dbi_base)) {
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long err = PTR_ERR(al_pcie->dbi_base);
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dev_err(dev, "couldn't remap dbi base %pR (err:%ld)\n",
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res, err);
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return err;
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}
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cfg->priv = al_pcie;
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return 0;
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}
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struct pci_ecam_ops al_pcie_ops = {
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.bus_shift = 20,
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.init = al_pcie_init,
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.pci_ops = {
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.map_bus = al_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
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