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The dwc2 IP on the SOCFPGA cannot use the default HW configured FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064 32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults to 0x2000 or 8192 32-bit words. So the driver cannot just use the fifo sizes as read from those registers. For platforms that face the same issue, this commits sets the RX, periodic TX, and non-periodic TX fifo size to those that are recommended v2.93a spec for the DWC2 IP. Implements Method #2 from the Synopsys v2.93a spec for the DWC2. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| core_intr.c | ||
| core.c | ||
| core.h | ||
| gadget.c | ||
| hcd_ddma.c | ||
| hcd_intr.c | ||
| hcd_queue.c | ||
| hcd.c | ||
| hcd.h | ||
| hw.h | ||
| Kconfig | ||
| Makefile | ||
| pci.c | ||
| platform.c | ||