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d4b05923f5
Our XSAVE features are divided into two categories: those that
generate FPU exceptions, and those that do not. MPX and pkeys do
not generate FPU exceptions and thus can not be used lazily. We
disable them when lazy mode is forced on.
We have a pair of masks to collect these two sets of features, but
XFEATURE_MASK_PKRU was added to the wrong mask: XFEATURE_MASK_LAZY.
Fix it by moving the feature to XFEATURE_MASK_EAGER.
Note: this only causes problem if you boot with lazy FPU mode
(eagerfpu=off) which is *not* the default. It also only affects
hardware which is not currently publicly available. It looks like
eager mode is going away, but we still need this patch applied
to any kernel that has protection keys and lazy mode, which is 4.6
through 4.8 at this point, and 4.9 if the lazy removal isn't sent
to Linus for 4.9.
Fixes: c8df400984 ("x86/fpu, x86/mm/pkeys: Add PKRU xsave fields and data structures")
Signed-off-by: Dave Hansen <dave.hansen@intel.com>
Cc: Dave Hansen <dave@sr71.net>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20161007162342.28A49813@viggo.jf.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
#ifndef __ASM_X86_XSAVE_H
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#define __ASM_X86_XSAVE_H
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#include <linux/types.h>
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#include <asm/processor.h>
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#include <linux/uaccess.h>
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/* Bit 63 of XCR0 is reserved for future expansion */
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#define XFEATURE_MASK_EXTEND (~(XFEATURE_MASK_FPSSE | (1ULL << 63)))
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#define XSTATE_CPUID 0x0000000d
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#define FXSAVE_SIZE 512
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#define XSAVE_HDR_SIZE 64
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#define XSAVE_HDR_OFFSET FXSAVE_SIZE
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#define XSAVE_YMM_SIZE 256
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#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
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/* Supervisor features */
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#define XFEATURE_MASK_SUPERVISOR (XFEATURE_MASK_PT)
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/* Supported features which support lazy state saving */
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#define XFEATURE_MASK_LAZY (XFEATURE_MASK_FP | \
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XFEATURE_MASK_SSE | \
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XFEATURE_MASK_YMM | \
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XFEATURE_MASK_OPMASK | \
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XFEATURE_MASK_ZMM_Hi256 | \
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XFEATURE_MASK_Hi16_ZMM)
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/* Supported features which require eager state saving */
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#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | \
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XFEATURE_MASK_BNDCSR | \
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XFEATURE_MASK_PKRU)
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/* All currently supported features */
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#define XCNTXT_MASK (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
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#ifdef CONFIG_X86_64
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#define REX_PREFIX "0x48, "
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#else
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#define REX_PREFIX
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#endif
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extern u64 xfeatures_mask;
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extern u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS];
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extern void __init update_regset_xstate_info(unsigned int size,
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u64 xstate_mask);
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void fpu__xstate_clear_all_cpu_caps(void);
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void *get_xsave_addr(struct xregs_state *xsave, int xstate);
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const void *get_xsave_field_ptr(int xstate_field);
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int using_compacted_format(void);
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int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf,
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void __user *ubuf, struct xregs_state *xsave);
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int copyin_to_xsaves(const void *kbuf, const void __user *ubuf,
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struct xregs_state *xsave);
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#endif
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