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d8725e38dd
Add the PCIe compatible string for LS1028A. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
66 lines
2.7 KiB
Plaintext
66 lines
2.7 KiB
Plaintext
Freescale Layerscape PCIe controller
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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This controller derives its clocks from the Reset Configuration Word (RCW)
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which is used to describe the PLL settings at the time of chip-reset.
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Also as per the available Reference Manuals, there is no specific 'version'
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register available in the Freescale PCIe controller register set,
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which can allow determining the underlying DesignWare PCIe controller version
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information.
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Required properties:
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- compatible: should contain the platform identifier such as:
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RC mode:
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"fsl,ls1021a-pcie"
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"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
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"fsl,ls2088a-pcie"
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"fsl,ls1088a-pcie"
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"fsl,ls1046a-pcie"
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"fsl,ls1043a-pcie"
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"fsl,ls1012a-pcie"
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"fsl,ls1028a-pcie"
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EP mode:
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"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The interrupt that is asserted for controller interrupts
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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This is used to get SCFG PEXN registers
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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Example:
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pcie@3400000 {
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compatible = "fsl,ls1021a-pcie";
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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};
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