mirror of
https://github.com/torvalds/linux.git
synced 2024-12-29 14:21:47 +00:00
5296bab33b
Add support for EDAC on the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1547743097-5236-3-git-send-email-schaecsn@gmx.net
26 lines
747 B
Plaintext
26 lines
747 B
Plaintext
Aspeed AST2500 SoC EDAC node
|
|
|
|
The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
|
|
correction check).
|
|
|
|
The memory controller supports SECDED (single bit error correction, double bit
|
|
error detection) and single bit error auto scrubbing by reserving 8 bits for
|
|
every 64 bit word (effectively reducing available memory to 8/9).
|
|
|
|
Note, the bootloader must configure ECC mode in the memory controller.
|
|
|
|
|
|
Required properties:
|
|
- compatible: should be "aspeed,ast2500-sdram-edac"
|
|
- reg: sdram controller register set should be <0x1e6e0000 0x174>
|
|
- interrupts: should be AVIC interrupt #0
|
|
|
|
|
|
Example:
|
|
|
|
edac: sdram@1e6e0000 {
|
|
compatible = "aspeed,ast2500-sdram-edac";
|
|
reg = <0x1e6e0000 0x174>;
|
|
interrupts = <0>;
|
|
};
|