linux/arch/x86/kvm/vmx
Marc Orr c73f4c998e KVM: x86: nVMX: fix x2APIC VTPR read intercept
Referring to the "VIRTUALIZING MSR-BASED APIC ACCESSES" chapter of the
SDM, when "virtualize x2APIC mode" is 1 and "APIC-register
virtualization" is 0, a RDMSR of 808H should return the VTPR from the
virtual APIC page.

However, for nested, KVM currently fails to disable the read intercept
for this MSR. This means that a RDMSR exit takes precedence over
"virtualize x2APIC mode", and KVM passes through L1's TPR to L2,
instead of sourcing the value from L2's virtual APIC page.

This patch fixes the issue by disabling the read intercept, in VMCS02,
for the VTPR when "APIC-register virtualization" is 0.

The issue described above and fix prescribed here, were verified with
a related patch in kvm-unit-tests titled "Test VMX's virtualize x2APIC
mode w/ nested".

Signed-off-by: Marc Orr <marcorr@google.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Fixes: c992384bde ("KVM: vmx: speed up MSR bitmap merge")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-04-05 21:08:30 +02:00
..
capabilities.h
evmcs.c x86/kvm/hyper-v: nested_enable_evmcs() sets vmcs_version incorrectly 2019-01-25 19:11:37 +01:00
evmcs.h
nested.c KVM: x86: nVMX: fix x2APIC VTPR read intercept 2019-04-05 21:08:30 +02:00
nested.h
ops.h
pmu_intel.c
vmcs12.c
vmcs12.h
vmcs_shadow_fields.h
vmcs.h KVM: nVMX: Cache host_rsp on a per-VMCS basis 2019-02-12 13:12:22 +01:00
vmenter.S KVM: VMX: Reorder clearing of registers in the vCPU-run assembly flow 2019-02-20 22:48:18 +01:00
vmx.c KVM: x86: Emulate MSR_IA32_ARCH_CAPABILITIES on AMD hosts 2019-03-28 17:29:00 +01:00
vmx.h KVM: x86: Emulate MSR_IA32_ARCH_CAPABILITIES on AMD hosts 2019-03-28 17:29:00 +01:00