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When kernel's binary becomes large enough (32M and more) errors may occur during the final linkage stage. It happens because the build system uses short relocations for ARC by default. This problem may be easily resolved by passing -mlong-calls option to GCC to use long absolute jumps (j) instead of short relative branchs (b). But there are fragments of pure assembler code exist which use branchs in inappropriate places and cause a linkage error because of relocations overflow. First of these fragments is .fixup insertion in futex.h and unaligned.c. It inserts a code in the separate section (.fixup) with branch instruction. It leads to the linkage error when kernel becomes large. Second of these fragments is calling scheduler's functions (common kernel code) from entry.S of ARC's code. When kernel's binary becomes large it may lead to the linkage error because scheduler may occur far enough from ARC's code in the final binary. Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
202 lines
4.3 KiB
C
202 lines
4.3 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: August 2010: From Android kernel work
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/preempt.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#ifdef CONFIG_ARC_HAS_LLSC
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)\
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\
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smp_mb(); \
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__asm__ __volatile__( \
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"1: llock %1, [%2] \n" \
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insn "\n" \
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"2: scond %0, [%2] \n" \
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" bnz 1b \n" \
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" mov %0, 0 \n" \
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"3: \n" \
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" .section .fixup,\"ax\" \n" \
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" .align 4 \n" \
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"4: mov %0, %4 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" .align 4 \n" \
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" .word 1b, 4b \n" \
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" .word 2b, 4b \n" \
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" .previous \n" \
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\
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: "=&r" (ret), "=&r" (oldval) \
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: "r" (uaddr), "r" (oparg), "ir" (-EFAULT) \
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: "cc", "memory"); \
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smp_mb() \
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#else /* !CONFIG_ARC_HAS_LLSC */
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)\
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\
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smp_mb(); \
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__asm__ __volatile__( \
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"1: ld %1, [%2] \n" \
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insn "\n" \
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"2: st %0, [%2] \n" \
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" mov %0, 0 \n" \
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"3: \n" \
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" .section .fixup,\"ax\" \n" \
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" .align 4 \n" \
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"4: mov %0, %4 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" .align 4 \n" \
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" .word 1b, 4b \n" \
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" .word 2b, 4b \n" \
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" .previous \n" \
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\
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: "=&r" (ret), "=&r" (oldval) \
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: "r" (uaddr), "r" (oparg), "ir" (-EFAULT) \
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: "cc", "memory"); \
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smp_mb() \
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#endif
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static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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#ifndef CONFIG_ARC_HAS_LLSC
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preempt_disable(); /* to guarantee atomic r-m-w of futex op */
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#endif
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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/* oldval = *uaddr; *uaddr += oparg ; ret = *uaddr */
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__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("bic %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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#ifndef CONFIG_ARC_HAS_LLSC
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preempt_enable();
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#endif
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ:
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ret = (oldval == cmparg);
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break;
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case FUTEX_OP_CMP_NE:
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ret = (oldval != cmparg);
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break;
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case FUTEX_OP_CMP_LT:
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ret = (oldval < cmparg);
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break;
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case FUTEX_OP_CMP_GE:
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ret = (oldval >= cmparg);
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break;
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case FUTEX_OP_CMP_LE:
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ret = (oldval <= cmparg);
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break;
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case FUTEX_OP_CMP_GT:
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ret = (oldval > cmparg);
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break;
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default:
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ret = -ENOSYS;
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}
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}
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return ret;
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}
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/*
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* cmpxchg of futex (pagefaults disabled by caller)
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* Return 0 for success, -EFAULT otherwise
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*/
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 expval,
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u32 newval)
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{
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int ret = 0;
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u32 existval;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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#ifndef CONFIG_ARC_HAS_LLSC
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preempt_disable(); /* to guarantee atomic r-m-w of futex op */
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#endif
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smp_mb();
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__asm__ __volatile__(
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#ifdef CONFIG_ARC_HAS_LLSC
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"1: llock %1, [%4] \n"
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" brne %1, %2, 3f \n"
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"2: scond %3, [%4] \n"
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" bnz 1b \n"
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#else
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"1: ld %1, [%4] \n"
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" brne %1, %2, 3f \n"
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"2: st %3, [%4] \n"
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#endif
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"3: \n"
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" .section .fixup,\"ax\" \n"
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"4: mov %0, %5 \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" .align 4 \n"
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" .word 1b, 4b \n"
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" .word 2b, 4b \n"
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" .previous\n"
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: "+&r"(ret), "=&r"(existval)
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: "r"(expval), "r"(newval), "r"(uaddr), "ir"(-EFAULT)
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: "cc", "memory");
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smp_mb();
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#ifndef CONFIG_ARC_HAS_LLSC
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preempt_enable();
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#endif
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*uval = existval;
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return ret;
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}
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#endif
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