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e6b5be2be4
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
1088 lines
31 KiB
C
1088 lines
31 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Arun R Murthy <arun.murthy@stericsson.com>
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* Author: Daniel Willerud <daniel.willerud@stericsson.com>
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* Author: Johan Palsson <johan.palsson@stericsson.com>
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_device.h>
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#include <linux/completion.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/mfd/abx500.h>
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#include <linux/mfd/abx500/ab8500.h>
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#include <linux/mfd/abx500/ab8500-gpadc.h>
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/*
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* GPADC register offsets
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* Bank : 0x0A
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*/
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#define AB8500_GPADC_CTRL1_REG 0x00
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#define AB8500_GPADC_CTRL2_REG 0x01
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#define AB8500_GPADC_CTRL3_REG 0x02
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#define AB8500_GPADC_AUTO_TIMER_REG 0x03
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#define AB8500_GPADC_STAT_REG 0x04
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#define AB8500_GPADC_MANDATAL_REG 0x05
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#define AB8500_GPADC_MANDATAH_REG 0x06
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#define AB8500_GPADC_AUTODATAL_REG 0x07
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#define AB8500_GPADC_AUTODATAH_REG 0x08
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#define AB8500_GPADC_MUX_CTRL_REG 0x09
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#define AB8540_GPADC_MANDATA2L_REG 0x09
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#define AB8540_GPADC_MANDATA2H_REG 0x0A
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#define AB8540_GPADC_APEAAX_REG 0x10
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#define AB8540_GPADC_APEAAT_REG 0x11
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#define AB8540_GPADC_APEAAM_REG 0x12
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#define AB8540_GPADC_APEAAH_REG 0x13
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#define AB8540_GPADC_APEAAL_REG 0x14
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/*
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* OTP register offsets
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* Bank : 0x15
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*/
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#define AB8500_GPADC_CAL_1 0x0F
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#define AB8500_GPADC_CAL_2 0x10
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#define AB8500_GPADC_CAL_3 0x11
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#define AB8500_GPADC_CAL_4 0x12
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#define AB8500_GPADC_CAL_5 0x13
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#define AB8500_GPADC_CAL_6 0x14
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#define AB8500_GPADC_CAL_7 0x15
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/* New calibration for 8540 */
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#define AB8540_GPADC_OTP4_REG_7 0x38
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#define AB8540_GPADC_OTP4_REG_6 0x39
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#define AB8540_GPADC_OTP4_REG_5 0x3A
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/* gpadc constants */
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#define EN_VINTCORE12 0x04
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#define EN_VTVOUT 0x02
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#define EN_GPADC 0x01
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#define DIS_GPADC 0x00
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#define AVG_1 0x00
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#define AVG_4 0x20
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#define AVG_8 0x40
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#define AVG_16 0x60
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#define ADC_SW_CONV 0x04
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#define EN_ICHAR 0x80
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#define BTEMP_PULL_UP 0x08
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#define EN_BUF 0x40
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#define DIS_ZERO 0x00
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#define GPADC_BUSY 0x01
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#define EN_FALLING 0x10
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#define EN_TRIG_EDGE 0x02
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#define EN_VBIAS_XTAL_TEMP 0x02
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/* GPADC constants from AB8500 spec, UM0836 */
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#define ADC_RESOLUTION 1024
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#define ADC_CH_BTEMP_MIN 0
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#define ADC_CH_BTEMP_MAX 1350
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#define ADC_CH_DIETEMP_MIN 0
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#define ADC_CH_DIETEMP_MAX 1350
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#define ADC_CH_CHG_V_MIN 0
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#define ADC_CH_CHG_V_MAX 20030
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#define ADC_CH_ACCDET2_MIN 0
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#define ADC_CH_ACCDET2_MAX 2500
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#define ADC_CH_VBAT_MIN 2300
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#define ADC_CH_VBAT_MAX 4800
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#define ADC_CH_CHG_I_MIN 0
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#define ADC_CH_CHG_I_MAX 1500
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#define ADC_CH_BKBAT_MIN 0
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#define ADC_CH_BKBAT_MAX 3200
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/* GPADC constants from AB8540 spec */
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#define ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat*/
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#define ADC_CH_IBAT_MAX 6000
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#define ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat*/
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#define ADC_CH_IBAT_MAX_V 60
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#define IBAT_VDROP_L (-56) /* mV */
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#define IBAT_VDROP_H 56
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/* This is used to not lose precision when dividing to get gain and offset */
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#define CALIB_SCALE 1000
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/*
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* Number of bits shift used to not lose precision
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* when dividing to get ibat gain.
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*/
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#define CALIB_SHIFT_IBAT 20
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/* Time in ms before disabling regulator */
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#define GPADC_AUDOSUSPEND_DELAY 1
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#define CONVERSION_TIME 500 /* ms */
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enum cal_channels {
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ADC_INPUT_VMAIN = 0,
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ADC_INPUT_BTEMP,
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ADC_INPUT_VBAT,
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ADC_INPUT_IBAT,
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NBR_CAL_INPUTS,
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};
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/**
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* struct adc_cal_data - Table for storing gain and offset for the calibrated
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* ADC channels
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* @gain: Gain of the ADC channel
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* @offset: Offset of the ADC channel
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*/
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struct adc_cal_data {
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s64 gain;
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s64 offset;
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u16 otp_calib_hi;
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u16 otp_calib_lo;
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};
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/**
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* struct ab8500_gpadc - AB8500 GPADC device information
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* @dev: pointer to the struct device
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* @node: a list of AB8500 GPADCs, hence prepared for
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reentrance
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* @parent: pointer to the struct ab8500
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* @ab8500_gpadc_complete: pointer to the struct completion, to indicate
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* the completion of gpadc conversion
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* @ab8500_gpadc_lock: structure of type mutex
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* @regu: pointer to the struct regulator
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* @irq_sw: interrupt number that is used by gpadc for Sw
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* conversion
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* @irq_hw: interrupt number that is used by gpadc for Hw
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* conversion
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* @cal_data array of ADC calibration data structs
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*/
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struct ab8500_gpadc {
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struct device *dev;
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struct list_head node;
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struct ab8500 *parent;
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struct completion ab8500_gpadc_complete;
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struct mutex ab8500_gpadc_lock;
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struct regulator *regu;
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int irq_sw;
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int irq_hw;
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struct adc_cal_data cal_data[NBR_CAL_INPUTS];
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};
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static LIST_HEAD(ab8500_gpadc_list);
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/**
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* ab8500_gpadc_get() - returns a reference to the primary AB8500 GPADC
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* (i.e. the first GPADC in the instance list)
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*/
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struct ab8500_gpadc *ab8500_gpadc_get(char *name)
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{
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struct ab8500_gpadc *gpadc;
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list_for_each_entry(gpadc, &ab8500_gpadc_list, node) {
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if (!strcmp(name, dev_name(gpadc->dev)))
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return gpadc;
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}
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(ab8500_gpadc_get);
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/**
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* ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
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*/
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int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, u8 channel,
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int ad_value)
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{
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int res;
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switch (channel) {
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case MAIN_CHARGER_V:
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/* For some reason we don't have calibrated data */
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if (!gpadc->cal_data[ADC_INPUT_VMAIN].gain) {
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res = ADC_CH_CHG_V_MIN + (ADC_CH_CHG_V_MAX -
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ADC_CH_CHG_V_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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}
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/* Here we can use the calibrated data */
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res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VMAIN].gain +
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gpadc->cal_data[ADC_INPUT_VMAIN].offset) / CALIB_SCALE;
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break;
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case XTAL_TEMP:
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case BAT_CTRL:
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case BTEMP_BALL:
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case ACC_DETECT1:
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case ADC_AUX1:
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case ADC_AUX2:
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/* For some reason we don't have calibrated data */
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if (!gpadc->cal_data[ADC_INPUT_BTEMP].gain) {
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res = ADC_CH_BTEMP_MIN + (ADC_CH_BTEMP_MAX -
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ADC_CH_BTEMP_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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}
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/* Here we can use the calibrated data */
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res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_BTEMP].gain +
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gpadc->cal_data[ADC_INPUT_BTEMP].offset) / CALIB_SCALE;
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break;
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case MAIN_BAT_V:
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case VBAT_TRUE_MEAS:
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/* For some reason we don't have calibrated data */
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if (!gpadc->cal_data[ADC_INPUT_VBAT].gain) {
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res = ADC_CH_VBAT_MIN + (ADC_CH_VBAT_MAX -
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ADC_CH_VBAT_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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}
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/* Here we can use the calibrated data */
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res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VBAT].gain +
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gpadc->cal_data[ADC_INPUT_VBAT].offset) / CALIB_SCALE;
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break;
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case DIE_TEMP:
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res = ADC_CH_DIETEMP_MIN +
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(ADC_CH_DIETEMP_MAX - ADC_CH_DIETEMP_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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case ACC_DETECT2:
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res = ADC_CH_ACCDET2_MIN +
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(ADC_CH_ACCDET2_MAX - ADC_CH_ACCDET2_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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case VBUS_V:
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res = ADC_CH_CHG_V_MIN +
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(ADC_CH_CHG_V_MAX - ADC_CH_CHG_V_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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case MAIN_CHARGER_C:
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case USB_CHARGER_C:
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res = ADC_CH_CHG_I_MIN +
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(ADC_CH_CHG_I_MAX - ADC_CH_CHG_I_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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case BK_BAT_V:
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res = ADC_CH_BKBAT_MIN +
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(ADC_CH_BKBAT_MAX - ADC_CH_BKBAT_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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case IBAT_VIRTUAL_CHANNEL:
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/* For some reason we don't have calibrated data */
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if (!gpadc->cal_data[ADC_INPUT_IBAT].gain) {
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res = ADC_CH_IBAT_MIN + (ADC_CH_IBAT_MAX -
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ADC_CH_IBAT_MIN) * ad_value /
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ADC_RESOLUTION;
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break;
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}
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/* Here we can use the calibrated data */
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res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_IBAT].gain +
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gpadc->cal_data[ADC_INPUT_IBAT].offset)
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>> CALIB_SHIFT_IBAT;
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break;
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default:
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dev_err(gpadc->dev,
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"unknown channel, not possible to convert\n");
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res = -EINVAL;
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break;
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}
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return res;
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}
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EXPORT_SYMBOL(ab8500_gpadc_ad_to_voltage);
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/**
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* ab8500_gpadc_sw_hw_convert() - gpadc conversion
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* @channel: analog channel to be converted to digital data
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* @avg_sample: number of ADC sample to average
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* @trig_egde: selected ADC trig edge
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* @trig_timer: selected ADC trigger delay timer
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* @conv_type: selected conversion type (HW or SW conversion)
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*
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* This function converts the selected analog i/p to digital
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* data.
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*/
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int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
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u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
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{
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int ad_value;
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int voltage;
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ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
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trig_edge, trig_timer, conv_type);
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/* On failure retry a second time */
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if (ad_value < 0)
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ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
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trig_edge, trig_timer, conv_type);
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if (ad_value < 0) {
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dev_err(gpadc->dev, "GPADC raw value failed ch: %d\n",
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channel);
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return ad_value;
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}
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voltage = ab8500_gpadc_ad_to_voltage(gpadc, channel, ad_value);
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if (voltage < 0)
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dev_err(gpadc->dev, "GPADC to voltage conversion failed ch:"
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" %d AD: 0x%x\n", channel, ad_value);
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return voltage;
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}
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EXPORT_SYMBOL(ab8500_gpadc_sw_hw_convert);
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/**
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* ab8500_gpadc_read_raw() - gpadc read
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* @channel: analog channel to be read
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* @avg_sample: number of ADC sample to average
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* @trig_edge: selected trig edge
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* @trig_timer: selected ADC trigger delay timer
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* @conv_type: selected conversion type (HW or SW conversion)
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*
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* This function obtains the raw ADC value for an hardware conversion,
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* this then needs to be converted by calling ab8500_gpadc_ad_to_voltage()
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*/
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int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
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u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
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{
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int raw_data;
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raw_data = ab8500_gpadc_double_read_raw(gpadc, channel,
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avg_sample, trig_edge, trig_timer, conv_type, NULL);
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return raw_data;
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}
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int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
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u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type,
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int *ibat)
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{
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int ret;
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int looplimit = 0;
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unsigned long completion_timeout;
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u8 val, low_data, high_data, low_data2, high_data2;
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u8 val_reg1 = 0;
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unsigned int delay_min = 0;
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unsigned int delay_max = 0;
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u8 data_low_addr, data_high_addr;
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if (!gpadc)
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return -ENODEV;
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/* check if convertion is supported */
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if ((gpadc->irq_sw < 0) && (conv_type == ADC_SW))
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return -ENOTSUPP;
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if ((gpadc->irq_hw < 0) && (conv_type == ADC_HW))
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return -ENOTSUPP;
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mutex_lock(&gpadc->ab8500_gpadc_lock);
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/* Enable VTVout LDO this is required for GPADC */
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pm_runtime_get_sync(gpadc->dev);
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|
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/* Check if ADC is not busy, lock and proceed */
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do {
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ret = abx500_get_register_interruptible(gpadc->dev,
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AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
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if (ret < 0)
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goto out;
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if (!(val & GPADC_BUSY))
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break;
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msleep(10);
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} while (++looplimit < 10);
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if (looplimit >= 10 && (val & GPADC_BUSY)) {
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dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
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ret = -EINVAL;
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goto out;
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}
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|
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/* Enable GPADC */
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val_reg1 |= EN_GPADC;
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|
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/* Select the channel source and set average samples */
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switch (avg_sample) {
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case SAMPLE_1:
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val = channel | AVG_1;
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break;
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case SAMPLE_4:
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val = channel | AVG_4;
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break;
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case SAMPLE_8:
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val = channel | AVG_8;
|
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break;
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default:
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val = channel | AVG_16;
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break;
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}
|
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|
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if (conv_type == ADC_HW) {
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ret = abx500_set_register_interruptible(gpadc->dev,
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AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val);
|
|
val_reg1 |= EN_TRIG_EDGE;
|
|
if (trig_edge)
|
|
val_reg1 |= EN_FALLING;
|
|
}
|
|
else
|
|
ret = abx500_set_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: set avg samples failed\n");
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Enable ADC, buffering, select rising edge and enable ADC path
|
|
* charging current sense if it needed, ABB 3.0 needs some special
|
|
* treatment too.
|
|
*/
|
|
switch (channel) {
|
|
case MAIN_CHARGER_C:
|
|
case USB_CHARGER_C:
|
|
val_reg1 |= EN_BUF | EN_ICHAR;
|
|
break;
|
|
case BTEMP_BALL:
|
|
if (!is_ab8500_2p0_or_earlier(gpadc->parent)) {
|
|
val_reg1 |= EN_BUF | BTEMP_PULL_UP;
|
|
/*
|
|
* Delay might be needed for ABB8500 cut 3.0, if not,
|
|
* remove when hardware will be availible
|
|
*/
|
|
delay_min = 1000; /* Delay in micro seconds */
|
|
delay_max = 10000; /* large range to optimise sleep mode */
|
|
break;
|
|
}
|
|
/* Intentional fallthrough */
|
|
default:
|
|
val_reg1 |= EN_BUF;
|
|
break;
|
|
}
|
|
|
|
/* Write configuration to register */
|
|
ret = abx500_set_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8500_GPADC_CTRL1_REG, val_reg1);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: set Control register failed\n");
|
|
goto out;
|
|
}
|
|
|
|
if (delay_min != 0)
|
|
usleep_range(delay_min, delay_max);
|
|
|
|
if (conv_type == ADC_HW) {
|
|
/* Set trigger delay timer */
|
|
ret = abx500_set_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, trig_timer);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: trig timer failed\n");
|
|
goto out;
|
|
}
|
|
completion_timeout = 2 * HZ;
|
|
data_low_addr = AB8500_GPADC_AUTODATAL_REG;
|
|
data_high_addr = AB8500_GPADC_AUTODATAH_REG;
|
|
} else {
|
|
/* Start SW conversion */
|
|
ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
|
|
ADC_SW_CONV, ADC_SW_CONV);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: start s/w conv failed\n");
|
|
goto out;
|
|
}
|
|
completion_timeout = msecs_to_jiffies(CONVERSION_TIME);
|
|
data_low_addr = AB8500_GPADC_MANDATAL_REG;
|
|
data_high_addr = AB8500_GPADC_MANDATAH_REG;
|
|
}
|
|
|
|
/* wait for completion of conversion */
|
|
if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
|
|
completion_timeout)) {
|
|
dev_err(gpadc->dev,
|
|
"timeout didn't receive GPADC conv interrupt\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Read the converted RAW data */
|
|
ret = abx500_get_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, data_low_addr, &low_data);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev, "gpadc_conversion: read low data failed\n");
|
|
goto out;
|
|
}
|
|
|
|
ret = abx500_get_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, data_high_addr, &high_data);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev, "gpadc_conversion: read high data failed\n");
|
|
goto out;
|
|
}
|
|
|
|
/* Check if double convertion is required */
|
|
if ((channel == BAT_CTRL_AND_IBAT) ||
|
|
(channel == VBAT_MEAS_AND_IBAT) ||
|
|
(channel == VBAT_TRUE_MEAS_AND_IBAT) ||
|
|
(channel == BAT_TEMP_AND_IBAT)) {
|
|
|
|
if (conv_type == ADC_HW) {
|
|
/* not supported */
|
|
ret = -ENOTSUPP;
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: only SW double conversion supported\n");
|
|
goto out;
|
|
} else {
|
|
/* Read the converted RAW data 2 */
|
|
ret = abx500_get_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG,
|
|
&low_data2);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: read sw low data 2 failed\n");
|
|
goto out;
|
|
}
|
|
|
|
ret = abx500_get_register_interruptible(gpadc->dev,
|
|
AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG,
|
|
&high_data2);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: read sw high data 2 failed\n");
|
|
goto out;
|
|
}
|
|
if (ibat != NULL) {
|
|
*ibat = (high_data2 << 8) | low_data2;
|
|
} else {
|
|
dev_warn(gpadc->dev,
|
|
"gpadc_conversion: ibat not stored\n");
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/* Disable GPADC */
|
|
ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
|
|
AB8500_GPADC_CTRL1_REG, DIS_GPADC);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
|
|
goto out;
|
|
}
|
|
|
|
/* Disable VTVout LDO this is required for GPADC */
|
|
pm_runtime_mark_last_busy(gpadc->dev);
|
|
pm_runtime_put_autosuspend(gpadc->dev);
|
|
|
|
mutex_unlock(&gpadc->ab8500_gpadc_lock);
|
|
|
|
return (high_data << 8) | low_data;
|
|
|
|
out:
|
|
/*
|
|
* It has shown to be needed to turn off the GPADC if an error occurs,
|
|
* otherwise we might have problem when waiting for the busy bit in the
|
|
* GPADC status register to go low. In V1.1 there wait_for_completion
|
|
* seems to timeout when waiting for an interrupt.. Not seen in V2.0
|
|
*/
|
|
(void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
|
|
AB8500_GPADC_CTRL1_REG, DIS_GPADC);
|
|
pm_runtime_put(gpadc->dev);
|
|
mutex_unlock(&gpadc->ab8500_gpadc_lock);
|
|
dev_err(gpadc->dev,
|
|
"gpadc_conversion: Failed to AD convert channel %d\n", channel);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(ab8500_gpadc_read_raw);
|
|
|
|
/**
|
|
* ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
|
|
* @irq: irq number
|
|
* @data: pointer to the data passed during request irq
|
|
*
|
|
* This is a interrupt service routine for gpadc conversion completion.
|
|
* Notifies the gpadc completion is completed and the converted raw value
|
|
* can be read from the registers.
|
|
* Returns IRQ status(IRQ_HANDLED)
|
|
*/
|
|
static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *_gpadc)
|
|
{
|
|
struct ab8500_gpadc *gpadc = _gpadc;
|
|
|
|
complete(&gpadc->ab8500_gpadc_complete);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int otp_cal_regs[] = {
|
|
AB8500_GPADC_CAL_1,
|
|
AB8500_GPADC_CAL_2,
|
|
AB8500_GPADC_CAL_3,
|
|
AB8500_GPADC_CAL_4,
|
|
AB8500_GPADC_CAL_5,
|
|
AB8500_GPADC_CAL_6,
|
|
AB8500_GPADC_CAL_7,
|
|
};
|
|
|
|
static int otp4_cal_regs[] = {
|
|
AB8540_GPADC_OTP4_REG_7,
|
|
AB8540_GPADC_OTP4_REG_6,
|
|
AB8540_GPADC_OTP4_REG_5,
|
|
};
|
|
|
|
static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
|
|
{
|
|
int i;
|
|
int ret[ARRAY_SIZE(otp_cal_regs)];
|
|
u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
|
|
int ret_otp4[ARRAY_SIZE(otp4_cal_regs)];
|
|
u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)];
|
|
int vmain_high, vmain_low;
|
|
int btemp_high, btemp_low;
|
|
int vbat_high, vbat_low;
|
|
int ibat_high, ibat_low;
|
|
s64 V_gain, V_offset, V2A_gain, V2A_offset;
|
|
struct ab8500 *ab8500;
|
|
|
|
ab8500 = gpadc->parent;
|
|
|
|
/* First we read all OTP registers and store the error code */
|
|
for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
|
|
ret[i] = abx500_get_register_interruptible(gpadc->dev,
|
|
AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
|
|
if (ret[i] < 0)
|
|
dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
|
|
__func__, otp_cal_regs[i]);
|
|
}
|
|
|
|
/*
|
|
* The ADC calibration data is stored in OTP registers.
|
|
* The layout of the calibration data is outlined below and a more
|
|
* detailed description can be found in UM0836
|
|
*
|
|
* vm_h/l = vmain_high/low
|
|
* bt_h/l = btemp_high/low
|
|
* vb_h/l = vbat_high/low
|
|
*
|
|
* Data bits 8500/9540:
|
|
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | | vm_h9 | vm_h8
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
*
|
|
* Data bits 8540:
|
|
* OTP2
|
|
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* |
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
*
|
|
* Data bits 8540:
|
|
* OTP4
|
|
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | | ib_h9 | ib_h8 | ib_h7
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5
|
|
* |.......|.......|.......|.......|.......|.......|.......|.......
|
|
* | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 |
|
|
*
|
|
*
|
|
* Ideal output ADC codes corresponding to injected input voltages
|
|
* during manufacturing is:
|
|
*
|
|
* vmain_high: Vin = 19500mV / ADC ideal code = 997
|
|
* vmain_low: Vin = 315mV / ADC ideal code = 16
|
|
* btemp_high: Vin = 1300mV / ADC ideal code = 985
|
|
* btemp_low: Vin = 21mV / ADC ideal code = 16
|
|
* vbat_high: Vin = 4700mV / ADC ideal code = 982
|
|
* vbat_low: Vin = 2380mV / ADC ideal code = 33
|
|
*/
|
|
|
|
if (is_ab8540(ab8500)) {
|
|
/* Calculate gain and offset for VMAIN if all reads succeeded*/
|
|
if (!(ret[1] < 0 || ret[2] < 0)) {
|
|
vmain_high = (((gpadc_cal[1] & 0xFF) << 2) |
|
|
((gpadc_cal[2] & 0xC0) >> 6));
|
|
vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
|
|
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi =
|
|
(u16)vmain_high;
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo =
|
|
(u16)vmain_low;
|
|
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
|
|
(19500 - 315) / (vmain_high - vmain_low);
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE *
|
|
19500 - (CALIB_SCALE * (19500 - 315) /
|
|
(vmain_high - vmain_low)) * vmain_high;
|
|
} else {
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
|
|
}
|
|
|
|
/* Read IBAT calibration Data */
|
|
for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) {
|
|
ret_otp4[i] = abx500_get_register_interruptible(
|
|
gpadc->dev, AB8500_OTP_EMUL,
|
|
otp4_cal_regs[i], &gpadc_otp4[i]);
|
|
if (ret_otp4[i] < 0)
|
|
dev_err(gpadc->dev,
|
|
"%s: read otp4 reg 0x%02x failed\n",
|
|
__func__, otp4_cal_regs[i]);
|
|
}
|
|
|
|
/* Calculate gain and offset for IBAT if all reads succeeded */
|
|
if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) {
|
|
ibat_high = (((gpadc_otp4[0] & 0x07) << 7) |
|
|
((gpadc_otp4[1] & 0xFE) >> 1));
|
|
ibat_low = (((gpadc_otp4[1] & 0x01) << 5) |
|
|
((gpadc_otp4[2] & 0xF8) >> 3));
|
|
|
|
gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi =
|
|
(u16)ibat_high;
|
|
gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo =
|
|
(u16)ibat_low;
|
|
|
|
V_gain = ((IBAT_VDROP_H - IBAT_VDROP_L)
|
|
<< CALIB_SHIFT_IBAT) / (ibat_high - ibat_low);
|
|
|
|
V_offset = (IBAT_VDROP_H << CALIB_SHIFT_IBAT) -
|
|
(((IBAT_VDROP_H - IBAT_VDROP_L) <<
|
|
CALIB_SHIFT_IBAT) / (ibat_high - ibat_low))
|
|
* ibat_high;
|
|
/*
|
|
* Result obtained is in mV (at a scale factor),
|
|
* we need to calculate gain and offset to get mA
|
|
*/
|
|
V2A_gain = (ADC_CH_IBAT_MAX - ADC_CH_IBAT_MIN)/
|
|
(ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V);
|
|
V2A_offset = ((ADC_CH_IBAT_MAX_V * ADC_CH_IBAT_MIN -
|
|
ADC_CH_IBAT_MAX * ADC_CH_IBAT_MIN_V)
|
|
<< CALIB_SHIFT_IBAT)
|
|
/ (ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V);
|
|
|
|
gpadc->cal_data[ADC_INPUT_IBAT].gain = V_gain * V2A_gain;
|
|
gpadc->cal_data[ADC_INPUT_IBAT].offset = V_offset *
|
|
V2A_gain + V2A_offset;
|
|
} else {
|
|
gpadc->cal_data[ADC_INPUT_IBAT].gain = 0;
|
|
}
|
|
|
|
dev_dbg(gpadc->dev, "IBAT gain %llu offset %llu\n",
|
|
gpadc->cal_data[ADC_INPUT_IBAT].gain,
|
|
gpadc->cal_data[ADC_INPUT_IBAT].offset);
|
|
} else {
|
|
/* Calculate gain and offset for VMAIN if all reads succeeded */
|
|
if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
|
|
vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
|
|
((gpadc_cal[1] & 0x3F) << 2) |
|
|
((gpadc_cal[2] & 0xC0) >> 6));
|
|
vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
|
|
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi =
|
|
(u16)vmain_high;
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo =
|
|
(u16)vmain_low;
|
|
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
|
|
(19500 - 315) / (vmain_high - vmain_low);
|
|
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE *
|
|
19500 - (CALIB_SCALE * (19500 - 315) /
|
|
(vmain_high - vmain_low)) * vmain_high;
|
|
} else {
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
|
|
}
|
|
}
|
|
|
|
/* Calculate gain and offset for BTEMP if all reads succeeded */
|
|
if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
|
|
btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
|
|
(gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7));
|
|
btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
|
|
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi = (u16)btemp_high;
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo = (u16)btemp_low;
|
|
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].gain =
|
|
CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].offset = CALIB_SCALE * 1300 -
|
|
(CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low))
|
|
* btemp_high;
|
|
} else {
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].gain = 0;
|
|
}
|
|
|
|
/* Calculate gain and offset for VBAT if all reads succeeded */
|
|
if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
|
|
vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
|
|
vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
|
|
|
|
gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi = (u16)vbat_high;
|
|
gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo = (u16)vbat_low;
|
|
|
|
gpadc->cal_data[ADC_INPUT_VBAT].gain = CALIB_SCALE *
|
|
(4700 - 2380) / (vbat_high - vbat_low);
|
|
gpadc->cal_data[ADC_INPUT_VBAT].offset = CALIB_SCALE * 4700 -
|
|
(CALIB_SCALE * (4700 - 2380) /
|
|
(vbat_high - vbat_low)) * vbat_high;
|
|
} else {
|
|
gpadc->cal_data[ADC_INPUT_VBAT].gain = 0;
|
|
}
|
|
|
|
dev_dbg(gpadc->dev, "VMAIN gain %llu offset %llu\n",
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].gain,
|
|
gpadc->cal_data[ADC_INPUT_VMAIN].offset);
|
|
|
|
dev_dbg(gpadc->dev, "BTEMP gain %llu offset %llu\n",
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].gain,
|
|
gpadc->cal_data[ADC_INPUT_BTEMP].offset);
|
|
|
|
dev_dbg(gpadc->dev, "VBAT gain %llu offset %llu\n",
|
|
gpadc->cal_data[ADC_INPUT_VBAT].gain,
|
|
gpadc->cal_data[ADC_INPUT_VBAT].offset);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int ab8500_gpadc_runtime_suspend(struct device *dev)
|
|
{
|
|
struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
|
|
|
|
regulator_disable(gpadc->regu);
|
|
return 0;
|
|
}
|
|
|
|
static int ab8500_gpadc_runtime_resume(struct device *dev)
|
|
{
|
|
struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = regulator_enable(gpadc->regu);
|
|
if (ret)
|
|
dev_err(dev, "Failed to enable vtvout LDO: %d\n", ret);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int ab8500_gpadc_suspend(struct device *dev)
|
|
{
|
|
struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
|
|
|
|
mutex_lock(&gpadc->ab8500_gpadc_lock);
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
regulator_disable(gpadc->regu);
|
|
return 0;
|
|
}
|
|
|
|
static int ab8500_gpadc_resume(struct device *dev)
|
|
{
|
|
struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = regulator_enable(gpadc->regu);
|
|
if (ret)
|
|
dev_err(dev, "Failed to enable vtvout LDO: %d\n", ret);
|
|
|
|
pm_runtime_mark_last_busy(gpadc->dev);
|
|
pm_runtime_put_autosuspend(gpadc->dev);
|
|
|
|
mutex_unlock(&gpadc->ab8500_gpadc_lock);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static int ab8500_gpadc_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
struct ab8500_gpadc *gpadc;
|
|
|
|
gpadc = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_gpadc), GFP_KERNEL);
|
|
if (!gpadc) {
|
|
dev_err(&pdev->dev, "Error: No memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
|
|
if (gpadc->irq_sw < 0)
|
|
dev_err(gpadc->dev, "failed to get platform sw_conv_end irq\n");
|
|
|
|
gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
|
|
if (gpadc->irq_hw < 0)
|
|
dev_err(gpadc->dev, "failed to get platform hw_conv_end irq\n");
|
|
|
|
gpadc->dev = &pdev->dev;
|
|
gpadc->parent = dev_get_drvdata(pdev->dev.parent);
|
|
mutex_init(&gpadc->ab8500_gpadc_lock);
|
|
|
|
/* Initialize completion used to notify completion of conversion */
|
|
init_completion(&gpadc->ab8500_gpadc_complete);
|
|
|
|
/* Register interrupts */
|
|
if (gpadc->irq_sw >= 0) {
|
|
ret = request_threaded_irq(gpadc->irq_sw, NULL,
|
|
ab8500_bm_gpadcconvend_handler,
|
|
IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-sw",
|
|
gpadc);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"Failed to register interrupt irq: %d\n",
|
|
gpadc->irq_sw);
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
if (gpadc->irq_hw >= 0) {
|
|
ret = request_threaded_irq(gpadc->irq_hw, NULL,
|
|
ab8500_bm_gpadcconvend_handler,
|
|
IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-hw",
|
|
gpadc);
|
|
if (ret < 0) {
|
|
dev_err(gpadc->dev,
|
|
"Failed to register interrupt irq: %d\n",
|
|
gpadc->irq_hw);
|
|
goto fail_irq;
|
|
}
|
|
}
|
|
|
|
/* VTVout LDO used to power up ab8500-GPADC */
|
|
gpadc->regu = devm_regulator_get(&pdev->dev, "vddadc");
|
|
if (IS_ERR(gpadc->regu)) {
|
|
ret = PTR_ERR(gpadc->regu);
|
|
dev_err(gpadc->dev, "failed to get vtvout LDO\n");
|
|
goto fail_irq;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, gpadc);
|
|
|
|
ret = regulator_enable(gpadc->regu);
|
|
if (ret) {
|
|
dev_err(gpadc->dev, "Failed to enable vtvout LDO: %d\n", ret);
|
|
goto fail_enable;
|
|
}
|
|
|
|
pm_runtime_set_autosuspend_delay(gpadc->dev, GPADC_AUDOSUSPEND_DELAY);
|
|
pm_runtime_use_autosuspend(gpadc->dev);
|
|
pm_runtime_set_active(gpadc->dev);
|
|
pm_runtime_enable(gpadc->dev);
|
|
|
|
ab8500_gpadc_read_calibration_data(gpadc);
|
|
list_add_tail(&gpadc->node, &ab8500_gpadc_list);
|
|
dev_dbg(gpadc->dev, "probe success\n");
|
|
|
|
return 0;
|
|
|
|
fail_enable:
|
|
fail_irq:
|
|
free_irq(gpadc->irq_sw, gpadc);
|
|
free_irq(gpadc->irq_hw, gpadc);
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
static int ab8500_gpadc_remove(struct platform_device *pdev)
|
|
{
|
|
struct ab8500_gpadc *gpadc = platform_get_drvdata(pdev);
|
|
|
|
/* remove this gpadc entry from the list */
|
|
list_del(&gpadc->node);
|
|
/* remove interrupt - completion of Sw ADC conversion */
|
|
if (gpadc->irq_sw >= 0)
|
|
free_irq(gpadc->irq_sw, gpadc);
|
|
if (gpadc->irq_hw >= 0)
|
|
free_irq(gpadc->irq_hw, gpadc);
|
|
|
|
pm_runtime_get_sync(gpadc->dev);
|
|
pm_runtime_disable(gpadc->dev);
|
|
|
|
regulator_disable(gpadc->regu);
|
|
|
|
pm_runtime_set_suspended(gpadc->dev);
|
|
|
|
pm_runtime_put_noidle(gpadc->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ab8500_gpadc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend,
|
|
ab8500_gpadc_runtime_resume,
|
|
NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(ab8500_gpadc_suspend,
|
|
ab8500_gpadc_resume)
|
|
|
|
};
|
|
|
|
static struct platform_driver ab8500_gpadc_driver = {
|
|
.probe = ab8500_gpadc_probe,
|
|
.remove = ab8500_gpadc_remove,
|
|
.driver = {
|
|
.name = "ab8500-gpadc",
|
|
.pm = &ab8500_gpadc_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init ab8500_gpadc_init(void)
|
|
{
|
|
return platform_driver_register(&ab8500_gpadc_driver);
|
|
}
|
|
|
|
static void __exit ab8500_gpadc_exit(void)
|
|
{
|
|
platform_driver_unregister(&ab8500_gpadc_driver);
|
|
}
|
|
|
|
/**
|
|
* ab8540_gpadc_get_otp() - returns OTP values
|
|
*
|
|
*/
|
|
void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
|
|
u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h,
|
|
u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h)
|
|
{
|
|
*vmain_l = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo;
|
|
*vmain_h = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi;
|
|
*btemp_l = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo;
|
|
*btemp_h = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi;
|
|
*vbat_l = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo;
|
|
*vbat_h = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi;
|
|
*ibat_l = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo;
|
|
*ibat_h = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi;
|
|
return ;
|
|
}
|
|
|
|
subsys_initcall_sync(ab8500_gpadc_init);
|
|
module_exit(ab8500_gpadc_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Arun R Murthy, Daniel Willerud, Johan Palsson,"
|
|
"M'boumba Cedric Madianga");
|
|
MODULE_ALIAS("platform:ab8500_gpadc");
|
|
MODULE_DESCRIPTION("AB8500 GPADC driver");
|