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9fde034864
Add a m68k-only set_fc helper to set the SFC and DFC registers for the few places that need to override it for special MM operations, but disconnect that from the deprecated kernel-wide set_fs() API. Note that the SFC/DFC registers are context switched, so there is no need to disable preemption. Partially based on an earlier patch from Linus Torvalds <torvalds@linux-foundation.org>. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Michael Schmitz <schmitzmic@gmail.com> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Link: https://lore.kernel.org/r/20210916070405.52750-7-hch@lst.de Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
128 lines
3.0 KiB
C
128 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/m68k/mm/cache.c
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*
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* Instruction cache handling
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/module.h>
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#include <asm/cacheflush.h>
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#include <asm/traps.h>
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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unsigned long paddr;
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/* The PLPAR instruction causes an access error if the translation
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* is not possible. To catch this we use the same exception mechanism
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* as for user space accesses in <asm/uaccess.h>. */
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asm volatile (".chip 68060\n"
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"1: plpar (%0)\n"
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".chip 68k\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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" .even\n"
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"3: sub.l %0,%0\n"
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" jra 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 1b,3b\n"
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".previous"
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: "=a" (paddr)
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: "0" (vaddr));
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return paddr;
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} else if (CPU_IS_040) {
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unsigned long mmusr;
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asm volatile (".chip 68040\n\t"
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"ptestr (%1)\n\t"
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"movec %%mmusr, %0\n\t"
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".chip 68k"
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: "=r" (mmusr)
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: "a" (vaddr));
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if (mmusr & MMU_R_040)
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return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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} else {
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WARN_ON_ONCE(!CPU_IS_040_OR_060);
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}
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return 0;
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}
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_user_range(unsigned long address, unsigned long endaddr)
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{
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if (CPU_IS_COLDFIRE) {
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unsigned long start, end;
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start = address & ICACHE_SET_MASK;
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end = endaddr & ICACHE_SET_MASK;
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if (start > end) {
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flush_cf_icache(0, end);
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end = ICACHE_MAX_ADDR;
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}
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flush_cf_icache(start, end);
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} else if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys_slow(address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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set_fc(SUPER_DATA);
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flush_icache_user_range(address, endaddr);
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set_fc(USER_DATA);
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}
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EXPORT_SYMBOL(flush_icache_range);
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void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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unsigned long start, end;
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start = addr & ICACHE_SET_MASK;
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end = (addr + len) & ICACHE_SET_MASK;
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if (start > end) {
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flush_cf_icache(0, end);
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end = ICACHE_MAX_ADDR;
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}
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flush_cf_icache(start, end);
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} else if (CPU_IS_040_OR_060) {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (page_to_phys(page)));
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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