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c32e00d909
The downstream kernel has infrastructure for passing votes from different interconnect nodes onto different RPMh RSCs. This neither implemented, not is going to be implemented upstream (in favor of a different solution using ICC tags through the same node). Unfortunately, as it happens, meaningless (in the upstream context) parts of the vendor driver were copied, ending up causing havoc - since all "per-RSC" (in quotes because they all point to the main APPS one) BCMs defined within the driver overwrite the value in RPMh on every aggregation. To both avoid keeping bogus code around and possibly introducing impossible-to-track-down bugs (busses shutting down for no reason), get rid of the duplicated BCMs and their associated ICC nodes. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-1-ce1272d77540@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
139 lines
4.9 KiB
C
139 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SM8450 interconnect IDs
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*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Linaro Limited
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
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#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
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#define SM8550_MASTER_A1NOC_SNOC 0
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#define SM8550_MASTER_A2NOC_SNOC 1
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#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
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#define SM8550_MASTER_APPSS_PROC 3
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#define SM8550_MASTER_CAMNOC_HF 4
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#define SM8550_MASTER_CAMNOC_ICP 5
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#define SM8550_MASTER_CAMNOC_SF 6
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#define SM8550_MASTER_CDSP_HCP 7
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#define SM8550_MASTER_CDSP_PROC 8
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#define SM8550_MASTER_CNOC_CFG 9
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#define SM8550_MASTER_CNOC_MNOC_CFG 10
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#define SM8550_MASTER_COMPUTE_NOC 11
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#define SM8550_MASTER_CRYPTO 12
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#define SM8550_MASTER_GEM_NOC_CNOC 13
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#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
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#define SM8550_MASTER_GFX3D 15
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#define SM8550_MASTER_GIC 16
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#define SM8550_MASTER_GIC_AHB 17
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#define SM8550_MASTER_GPU_TCU 18
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#define SM8550_MASTER_IPA 19
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#define SM8550_MASTER_LLCC 20
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#define SM8550_MASTER_LPASS_GEM_NOC 21
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#define SM8550_MASTER_LPASS_LPINOC 22
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#define SM8550_MASTER_LPASS_PROC 23
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#define SM8550_MASTER_LPIAON_NOC 24
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#define SM8550_MASTER_MDP 25
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#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
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#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
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#define SM8550_MASTER_MSS_PROC 28
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#define SM8550_MASTER_PCIE_0 29
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#define SM8550_MASTER_PCIE_1 30
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#define SM8550_MASTER_PCIE_ANOC_CFG 31
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#define SM8550_MASTER_QDSS_BAM 32
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#define SM8550_MASTER_QDSS_ETR 33
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#define SM8550_MASTER_QDSS_ETR_1 34
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#define SM8550_MASTER_QSPI_0 35
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#define SM8550_MASTER_QUP_1 36
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#define SM8550_MASTER_QUP_2 37
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#define SM8550_MASTER_QUP_CORE_0 38
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#define SM8550_MASTER_QUP_CORE_1 39
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#define SM8550_MASTER_QUP_CORE_2 40
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#define SM8550_MASTER_SDCC_2 41
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#define SM8550_MASTER_SDCC_4 42
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#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
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#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
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#define SM8550_MASTER_SP 45
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#define SM8550_MASTER_SYS_TCU 46
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#define SM8550_MASTER_UFS_MEM 47
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#define SM8550_MASTER_USB3_0 48
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#define SM8550_MASTER_VIDEO 49
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#define SM8550_MASTER_VIDEO_CV_PROC 50
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#define SM8550_MASTER_VIDEO_PROC 51
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#define SM8550_MASTER_VIDEO_V_PROC 52
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#define SM8550_SLAVE_A1NOC_SNOC 53
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#define SM8550_SLAVE_A2NOC_SNOC 54
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#define SM8550_SLAVE_AHB2PHY_NORTH 55
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#define SM8550_SLAVE_AHB2PHY_SOUTH 56
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#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
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#define SM8550_SLAVE_AOSS 58
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#define SM8550_SLAVE_APPSS 59
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#define SM8550_SLAVE_BOOT_IMEM 60
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#define SM8550_SLAVE_CAMERA_CFG 61
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#define SM8550_SLAVE_CDSP_MEM_NOC 62
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#define SM8550_SLAVE_CLK_CTL 63
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#define SM8550_SLAVE_CNOC_CFG 64
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#define SM8550_SLAVE_CNOC_MNOC_CFG 65
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#define SM8550_SLAVE_CNOC_MSS 66
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#define SM8550_SLAVE_CPR_NSPCX 67
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#define SM8550_SLAVE_CRYPTO_0_CFG 68
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#define SM8550_SLAVE_CX_RDPM 69
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#define SM8550_SLAVE_DDRSS_CFG 70
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#define SM8550_SLAVE_DISPLAY_CFG 71
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#define SM8550_SLAVE_EBI1 72
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#define SM8550_SLAVE_GEM_NOC_CNOC 73
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#define SM8550_SLAVE_GFX3D_CFG 74
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#define SM8550_SLAVE_I2C 75
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#define SM8550_SLAVE_IMEM 76
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#define SM8550_SLAVE_IMEM_CFG 77
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#define SM8550_SLAVE_IPA_CFG 78
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#define SM8550_SLAVE_IPC_ROUTER_CFG 79
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#define SM8550_SLAVE_LLCC 80
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#define SM8550_SLAVE_LPASS_GEM_NOC 81
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#define SM8550_SLAVE_LPASS_QTB_CFG 82
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#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
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#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
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#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
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#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
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#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
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#define SM8550_SLAVE_MX_RDPM 88
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#define SM8550_SLAVE_NSP_QTB_CFG 89
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#define SM8550_SLAVE_PCIE_0 90
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#define SM8550_SLAVE_PCIE_0_CFG 91
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#define SM8550_SLAVE_PCIE_1 92
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#define SM8550_SLAVE_PCIE_1_CFG 93
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#define SM8550_SLAVE_PCIE_ANOC_CFG 94
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#define SM8550_SLAVE_PDM 95
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#define SM8550_SLAVE_PIMEM_CFG 96
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#define SM8550_SLAVE_PRNG 97
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#define SM8550_SLAVE_QDSS_CFG 98
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#define SM8550_SLAVE_QDSS_STM 99
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#define SM8550_SLAVE_QSPI_0 100
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#define SM8550_SLAVE_QUP_1 101
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#define SM8550_SLAVE_QUP_2 102
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#define SM8550_SLAVE_QUP_CORE_0 103
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#define SM8550_SLAVE_QUP_CORE_1 104
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#define SM8550_SLAVE_QUP_CORE_2 105
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#define SM8550_SLAVE_RBCPR_CX_CFG 106
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#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
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#define SM8550_SLAVE_RBCPR_MXA_CFG 108
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#define SM8550_SLAVE_RBCPR_MXC_CFG 109
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#define SM8550_SLAVE_SDCC_2 110
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#define SM8550_SLAVE_SDCC_4 111
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#define SM8550_SLAVE_SERVICE_MNOC 112
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#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
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#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
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#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
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#define SM8550_SLAVE_SPSS_CFG 116
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#define SM8550_SLAVE_TCSR 117
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#define SM8550_SLAVE_TCU 118
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#define SM8550_SLAVE_TLMM 119
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#define SM8550_SLAVE_TME_CFG 120
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#define SM8550_SLAVE_UFS_MEM_CFG 121
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#define SM8550_SLAVE_USB3_0 122
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#define SM8550_SLAVE_VENUS_CFG 123
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#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
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#endif
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