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c4d06d2d20
Add port management message for setting Rx mode in the card, used for rx_mode netdev operation. The link event handler is used for getting a notification about the link state. Signed-off-by: Aviad Krawczyk <aviad.krawczyk@huawei.com> Signed-off-by: Zhao Chen <zhaochen6@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
237 lines
8.5 KiB
C
237 lines
8.5 KiB
C
/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#ifndef HINIC_HW_IF_H
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#define HINIC_HW_IF_H
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#define HINIC_DMA_ATTR_ST_SHIFT 0
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#define HINIC_DMA_ATTR_AT_SHIFT 8
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#define HINIC_DMA_ATTR_PH_SHIFT 10
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#define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12
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#define HINIC_DMA_ATTR_TPH_EN_SHIFT 13
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#define HINIC_DMA_ATTR_ST_MASK 0xFF
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#define HINIC_DMA_ATTR_AT_MASK 0x3
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#define HINIC_DMA_ATTR_PH_MASK 0x3
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#define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1
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#define HINIC_DMA_ATTR_TPH_EN_MASK 0x1
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#define HINIC_DMA_ATTR_SET(val, member) \
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(((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \
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HINIC_DMA_ATTR_##member##_SHIFT)
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#define HINIC_DMA_ATTR_CLEAR(val, member) \
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((val) & (~(HINIC_DMA_ATTR_##member##_MASK \
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<< HINIC_DMA_ATTR_##member##_SHIFT)))
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#define HINIC_FA0_FUNC_IDX_SHIFT 0
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#define HINIC_FA0_PF_IDX_SHIFT 10
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#define HINIC_FA0_PCI_INTF_IDX_SHIFT 14
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/* reserved members - off 16 */
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#define HINIC_FA0_FUNC_TYPE_SHIFT 24
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#define HINIC_FA0_FUNC_IDX_MASK 0x3FF
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#define HINIC_FA0_PF_IDX_MASK 0xF
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#define HINIC_FA0_PCI_INTF_IDX_MASK 0x3
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#define HINIC_FA0_FUNC_TYPE_MASK 0x1
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#define HINIC_FA0_GET(val, member) \
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(((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
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#define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8
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/* reserved members - off 10 */
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#define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12
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/* reserved members - off 15 */
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#define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20
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#define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24
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/* reserved members - off 27 */
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#define HINIC_FA1_INIT_STATUS_SHIFT 30
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#define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3
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#define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7
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#define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF
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#define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7
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#define HINIC_FA1_INIT_STATUS_MASK 0x1
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#define HINIC_FA1_GET(val, member) \
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(((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
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#define HINIC_FA5_PF_ACTION_SHIFT 0
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#define HINIC_FA5_PF_ACTION_MASK 0xFFFF
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#define HINIC_FA5_SET(val, member) \
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(((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)
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#define HINIC_FA5_CLEAR(val, member) \
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((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))
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#define HINIC_PPF_ELECTION_IDX_SHIFT 0
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#define HINIC_PPF_ELECTION_IDX_MASK 0x1F
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#define HINIC_PPF_ELECTION_SET(val, member) \
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(((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \
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HINIC_PPF_ELECTION_##member##_SHIFT)
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#define HINIC_PPF_ELECTION_GET(val, member) \
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(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
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HINIC_PPF_ELECTION_##member##_MASK)
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#define HINIC_PPF_ELECTION_CLEAR(val, member) \
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((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
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<< HINIC_PPF_ELECTION_##member##_SHIFT)))
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#define HINIC_MSIX_PENDING_LIMIT_SHIFT 0
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#define HINIC_MSIX_COALESC_TIMER_SHIFT 8
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#define HINIC_MSIX_LLI_TIMER_SHIFT 16
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#define HINIC_MSIX_LLI_CREDIT_SHIFT 24
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#define HINIC_MSIX_RESEND_TIMER_SHIFT 29
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#define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF
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#define HINIC_MSIX_COALESC_TIMER_MASK 0xFF
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#define HINIC_MSIX_LLI_TIMER_MASK 0xFF
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#define HINIC_MSIX_LLI_CREDIT_MASK 0x1F
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#define HINIC_MSIX_RESEND_TIMER_MASK 0x7
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#define HINIC_MSIX_ATTR_SET(val, member) \
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(((u32)(val) & HINIC_MSIX_##member##_MASK) << \
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HINIC_MSIX_##member##_SHIFT)
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#define HINIC_MSIX_ATTR_GET(val, member) \
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(((val) >> HINIC_MSIX_##member##_SHIFT) & \
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HINIC_MSIX_##member##_MASK)
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#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
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#define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1
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#define HINIC_MSIX_CNT_SET(val, member) \
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(((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \
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HINIC_MSIX_CNT_##member##_SHIFT)
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#define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)
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#define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)
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#define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)
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#define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)
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#define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)
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#define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)
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#define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)
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#define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
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#define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
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#define HINIC_PCI_CFG_REGS_BAR 0
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#define HINIC_PCIE_ST_DISABLE 0
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#define HINIC_PCIE_AT_DISABLE 0
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#define HINIC_PCIE_PH_DISABLE 0
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#define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */
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#define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */
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#define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */
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#define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */
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#define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */
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enum hinic_pcie_nosnoop {
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HINIC_PCIE_SNOOP = 0,
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HINIC_PCIE_NO_SNOOP = 1,
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};
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enum hinic_pcie_tph {
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HINIC_PCIE_TPH_DISABLE = 0,
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HINIC_PCIE_TPH_ENABLE = 1,
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};
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enum hinic_func_type {
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HINIC_PF = 0,
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HINIC_PPF = 2,
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};
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enum hinic_mod_type {
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HINIC_MOD_COMM = 0, /* HW communication module */
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HINIC_MOD_L2NIC = 1, /* L2NIC module */
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HINIC_MOD_CFGM = 7, /* Configuration module */
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HINIC_MOD_MAX = 15
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};
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enum hinic_node_id {
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HINIC_NODE_ID_MGMT = 21,
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};
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enum hinic_pf_action {
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HINIC_PF_MGMT_INIT = 0x0,
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HINIC_PF_MGMT_ACTIVE = 0x11,
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};
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struct hinic_func_attr {
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u16 func_idx;
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u8 pf_idx;
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u8 pci_intf_idx;
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enum hinic_func_type func_type;
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u8 ppf_idx;
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u16 num_irqs;
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u8 num_aeqs;
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u8 num_ceqs;
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u8 num_dma_attr;
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};
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struct hinic_hwif {
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struct pci_dev *pdev;
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void __iomem *cfg_regs_bar;
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struct hinic_func_attr attr;
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};
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static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
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{
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return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
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}
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static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
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u32 val)
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{
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writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
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}
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int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
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u8 pending_limit, u8 coalesc_timer,
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u8 lli_timer_cfg, u8 lli_credit_limit,
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u8 resend_timer);
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int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
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u8 *pending_limit, u8 *coalesc_timer_cfg,
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u8 *lli_timer, u8 *lli_credit_limit,
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u8 *resend_timer);
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int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
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void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
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int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);
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void hinic_free_hwif(struct hinic_hwif *hwif);
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#endif
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