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8997de30ad
Commit 58bac7b8de failed to move the two
PLL files s3c2440-pll-12000000.c and s3c2440-pll-16934400.c, so place
these in arch/arm/mach-s3c2440 to fix this commit up.
As a note, these are not built by the default configuration and thus the
failure to move wasn't spotted until much later.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
98 lines
3.8 KiB
C
98 lines
3.8 KiB
C
/* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
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*
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* Copyright (c) 2006-2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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* Vincent Sanders <vince@arm.linux.org.uk>
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*
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* S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
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{ .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
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{ .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
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{ .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
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{ .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
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{ .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
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{ .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
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{ .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
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{ .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
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{ .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
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{ .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
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{ .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
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{ .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
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{ .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
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{ .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
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{ .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
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{ .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
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{ .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
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{ .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
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{ .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
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{ .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
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{ .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
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{ .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
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{ .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
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{ .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
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{ .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
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{ .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
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{ .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
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};
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static int s3c2440_plls12_add(struct sys_device *dev)
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{
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struct clk *xtal_clk;
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unsigned long xtal;
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xtal_clk = clk_get(NULL, "xtal");
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if (IS_ERR(xtal_clk))
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return PTR_ERR(xtal_clk);
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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if (xtal == 12000000) {
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printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
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return s3c_plltab_register(s3c2440_plls_12,
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ARRAY_SIZE(s3c2440_plls_12));
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}
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return 0;
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}
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static struct sysdev_driver s3c2440_plls12_drv = {
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.add = s3c2440_plls12_add,
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};
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static int __init s3c2440_pll_12mhz(void)
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{
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return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
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}
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arch_initcall(s3c2440_pll_12mhz);
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static struct sysdev_driver s3c2442_plls12_drv = {
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.add = s3c2440_plls12_add,
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};
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static int __init s3c2442_pll_12mhz(void)
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{
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return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
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}
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arch_initcall(s3c2442_pll_12mhz);
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