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15cea99306
The wl1271 device is using a reference clock that may change between board to board. Make the ref_clock parameter configurable by board settings instead of having a hard coded value in the sources. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __BOOT_H__
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#define __BOOT_H__
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#include "wl1271.h"
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int wl1271_boot(struct wl1271 *wl);
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#define WL1271_NO_SUBBANDS 8
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#define WL1271_NO_POWER_LEVELS 4
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#define WL1271_FW_VERSION_MAX_LEN 20
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struct wl1271_static_data {
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u8 mac_address[ETH_ALEN];
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u8 padding[2];
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u8 fw_version[WL1271_FW_VERSION_MAX_LEN];
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u32 hw_version;
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u8 tx_power_table[WL1271_NO_SUBBANDS][WL1271_NO_POWER_LEVELS];
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};
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/* number of times we try to read the INIT interrupt */
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#define INIT_LOOP 20000
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/* delay between retries */
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#define INIT_LOOP_DELAY 50
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#define WU_COUNTER_PAUSE_VAL 0x3FF
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#define WELP_ARM_COMMAND_VAL 0x4
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#define OCP_REG_POLARITY 0x0064
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#define OCP_REG_CLK_TYPE 0x0448
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#define OCP_REG_CLK_POLARITY 0x0cb2
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#define OCP_REG_CLK_PULL 0x0cb4
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#define REG_FUSE_DATA_2_1 0x050a
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#define PG_VER_MASK 0x3c
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#define PG_VER_OFFSET 2
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#define CMD_MBOX_ADDRESS 0x407B4
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#define POLARITY_LOW BIT(1)
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#define NO_PULL (BIT(14) | BIT(15))
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#define FREF_CLK_TYPE_BITS 0xfffffe7f
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#define CLK_REQ_PRCM 0x100
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#define FREF_CLK_POLARITY_BITS 0xfffff8ff
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#define CLK_REQ_OUTN_SEL 0x700
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#endif
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